ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 405

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

31.4
31.4.1
31.4.2
8331A–AVR–07/11
JTAG Instructions
EXTEST; 0x1
IDCODE; 0x3
As shown in the state diagram, the run test/idle state need not be entered between selecting
JTAG instructions and using data registers.
Note: Independently of the initial state of the TAP controller, the test logic reset state can always
be entered by holding TMS high for five TCK clock periods.
The instruction register is four bits wide. Listed below are the JTAG instructions for boundary
scan operation and the PDICOM instruction used for accessing the PDI in JTAG mode.
The lsb is shifted in and out first for all shift registers.
The opcode for each instruction is shown beside the instruction name in hex format. The text
describes which data register is selected as the path between TDI and TDO for each instruction.
EXTEST is the instruction for selecting the boundary scan chain as the data register for testing
circuitry external to the AVR XMEGA device package. The instruction is used for sampling exter-
nal pins and loading output pins with data. For the I/O port pins, both output control (DIR) and
output data (OUT) are controllable via the scan chain, while the output control and actual pin
value are observable. The contents of the latched outputs of the boundary scan chain are driven
out as soon as the JTAG instruction register is loaded with the EXTEST instruction.
The active states are:
IDCODE is the instruction for selecting the 32-bit ID register as the data register. The ID register
consists of a version number, a device number, and the manufacturer code chosen by the Joint
Electron Devices Engineering Council (JEDEC). This is the default instruction after power up.
• Apply the TMS sequence 1, 1, 0 to reenter the run test/idle state. The instruction is latched
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the shift data
• Apply the TMS sequence 1, 1, 0 to reenter the run test/idle state. If the selected data register
• Capture DR: Data on the external pins are sampled into the boundary scan chain
• Shift DR: Data in the Boundary-scan Chain are shifted by the TCK input
• Update DR: Data from the scan chain are applied to output pins
TDO pin. The JTAG instruction selects a particular data register as the path between TDI and
TDO and controls the circuitry surrounding the selected data register
onto the parallel output from the shift register path in the update IR state. The exit IR, pause
IR, and exit2 IR states are used only for navigating the state machine
register, or shift DR, state. While in this state, upload the selected data register (selected by
the present JTAG instruction in the JTAG instruction register) from the TDI input at the rising
edge of TCK. In order to remain in the shift DR state, the TMS input must be held low during
the input of all bits except the msb. The msb of the data is shifted in when this state is left by
setting TMS high. While the data register is shifted in from the TDI pin, the parallel inputs to
the data register captured in the capture DR state are shifted out on the TDO pin
has a latched parallel output, the latching takes place in the update DR state. The exit DR,
pause DR, and exit2 DR states are used only for navigating the state machine.
Atmel AVR XMEGA AU
405