ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 344

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.10.2
8331A–AVR–07/11
SDRAMCTRLA – SDRAM Control Register A
• Bit 1:0 – IFMODE[1:0]: Interface Mode
These bits select EBI interface mode and the number of ports that should be enabled and over-
ridden for EBI, according to
Table 27-11. EBI Mode
• Bit 7:4 – Reserved
These bits are reserved and will always be read as zero.
• Bit 3 – SDCAS: SDRAM CAS Latency
This bit sets the CAS latency as a number of Clk
CAS latency is two Clk
cycles.
Table 27-12. SDRAM CAS Latency
• Bit 2 – SDROW: SDRAM Row Bits
This bit sets the number of row bit used for the connected SDRAM. By default this bit is zero,
and the row bit setting is set to 11 Row Bits. When this bit is set to one the row bit setting is set
to 12 Row Bits.
Table 27-13. SDRAM Row Bits
• Bit 1:0 – SDCOL[1:0]: SDRAM Column Bits
These bits select the number of column bits that are used for the connected SDRAM according
to
Bit
+0x01
Read/Write
Initial Value
table.Table 27-14 on page
IFMODE[1:0]
SDROW
SDROW
00
01
10
11
0
1
0
1
R
7
–
0
R
PER2
6
–
0
Group Configuration
DISABLED
3PORT
4PORT
2PORT
Group Configuration
2CLK
3CLK
Group Configuration
11BIT
12BIT
cycles. When this bit is set to one, the CAS latency is three Clk
Table 27-11 on page
345.
R
5
–
0
R
4
–
0
Description
EBI Disabled
EBI enabled with 3-port interface
EBI enabled with 4-port interface
EBI enabled with 2-port interface
SDCAS
Description
2 Clk
3 Clk
Description
11 Row bits
12 Row bits
R/W
3
0
344.
PER2
PER2
PER2
Atmel AVR XMEGA AU
cycles. By default this bit is zero and the
cycles delay
cycles delay
SDROW
R/W
2
0
R/W
1
0
SDCOL[1:0]
R/W
0
0
SDRAMCTRLA
PER2
344