ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 248

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.13.7
20.13.8
20.13.9
8331A–AVR–07/11
EPPTRL – Endpoint Configuration Table Pointer Low byte
EPPTRH – Endpoint Configuration Table Pointer High byte
INTCTRLA – Interrupt Control Register A
The EPPTRL and EPPTRH registers represent the 16-bit value EPPTR that contains the
address to the endpoint configuration table. The pointer to the endpoint configuration table must
be aligned to a 16-bit word, i.e. EPPTR[0] must be zero. Only the number of bits required to
address the available internal SRAM memory is implemented for each device. Unused bits will
always be read as zero.
• Bit 7:0 – EPPTR[7:0]: Endpoint Configuration Table Pointer
This register contains the 8 LSB of the Endpoint Configuration Table Pointer (EPPTR).
• Bit 7:0 – EPPTR[15:8]: Endpoint Configuration Table Pointer
This register contains the 8 MSB of the Endpoint Configuration Table Pointer (EPPTR).
• Bit 7 – SOFIE: Start Of Frame Interrupt Enable
Setting this bit enables the Start Of Frame (SOF) interrupt for the conditions that set the Start Of
Frame Interrupt Flag (SOFIF) in the INTFLAGSACLR/ INTFLAGSASET register. The INTLVL
bits must be non-zero for the interrupts to be generated.
• Bit 6 – BUSEVIE: Bus Event Interrupt Enable
Setting this bit will enable the interrupt for the following three different bus events:
The INTLVL bits must be non-zero for the interrupts to be generated.
Bit
+0x06
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
Bit
+0x07
Read/Write
Initial Value
1. Suspend: An interrupt will be generated for the conditions that set the Suspend Inter-
2. Resume: An interrupt will be generated for the conditions that set the Resume Interrupt
3. Reset: An interrupt will be generated for the conditions that set the Reset Interrupt Flag
rupt Flag (SUSPENDIF) in the INTFLAGSACLR/SET register.
Flag (RESUMEIF) in the INTFLAGSACLR/SET register.
(RESETIF) in the INTFLAGSACLR/SET register.
SOFIE
R/W
R/W
R/W
7
0
7
0
7
0
BUSEVIE
R/W
R/W
R/W
6
0
6
0
6
0
BUSERRIE
R/W
R/W
R/W
5
0
5
0
5
0
STALLIE
R/W
R/W
R/W
4
0
4
0
4
0
EPPTR[15:8]
EPPTR[7:0]
Atmel AVR XMEGA AU
R/W
R/W
3
0
3
0
R
3
–
0
R/W
R/W
2
0
2
0
R
2
–
0
R/W
R/W
R/W
1
0
1
0
1
0
INTLVL[1:0]
R/W
R/W
R
0
0
0
0
0
0
INTCTRLA
EPPTRH
EPPTRL
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