ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 365

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.11 DMA transfer
28.12 Interrupts and events
28.13 Calibration
28.14 Channel priority
28.15 Synchronous sampling
8331A–AVR–07/11
The DMA Controller can be used to transfer ADC conversion results to memory or other periph-
erals. A new conversion result for any of the ADC Channels can trigger a DMA transaction.
Refer to
transfers.
The ADC can generate interrupt requests and events. Each ADC channel has individual inter-
rupt settings and interrupt vectors. Interrupt requests and events can be generated when an
ADC conversion is complete, or if an ADC measurement is above or below the ADC Compare
register value.
The ADC has built-in linearity calibration. The value from the production test calibration, must be
loaded from the signature row and into the ADC calibration register from software for 12-bit
accuracy to be achievable. Offset and gain calibration must be done in software.
Since the Peripheral Clock is faster than the ADC clock, it is possible to set the start conversion
bit for several ADC channels within the same ADC clock period. Events may also trigger conver-
sions on several ADC channels and give the same scenario. In this case the ADC Channel with
the lowest number will be prioritized. This is shown the timing diagrams in
version Timing” on page
Starting an ADC conversion can cause unknown delay between the start trigger or event and the
actual conversion start since conversions of higher priority ADC channels can be pending, or
since the peripheral clock is faster than the ADC Clock. To start an ADC conversion immediately
on an incoming event, it is possible to flush the ADC for all measurements, reset the ADC clock
and start the conversion at the next Peripheral clock cycle (which then will also be the next ADC
clock cycle). If this is done all ongoing conversions in the ADC pipeline will be lost.
The ADC can be flushed from software, or an incoming event can do this automatically. When
this function is used the time between each conversion start trigger must be longer than the ADC
propagation delay to ensure that one conversion is finished before the ADC pipeline is flushed
and the next conversion is started.
It is also important to clear pending events or start adc conversion commands before doing a
flush. If not, pending conversions will start immediately after the flush.
In devices with two ADC peripherals, it is possible to start two ADC samples synchronously in
the two ADCs by using the same event channel to trigger both ADCs.
”DMAC - Direct Memory Access Controller” on page 53
360.
Atmel AVR XMEGA AU
for more details on DMA
”ADC Clock and Con-
365