ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 385

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.10 Register Description
29.10.1
29.10.2
8331A–AVR–07/11
CTRLA – Control Register A
CTRLB – Control Register B
• Bit 7:5 – Reserved
These bite are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 – IDOEN: DAC Internal Output Enable
Setting this bit will enable the internal DAC channel 0 output to be used by the Analog Compara-
tor and ADC. This will then also disable the pin output for DAC Channel 0.
• Bit 3 – CH1EN: DAC Channel 1 Output Enable
Setting this bit will make channel 1 available on pin.
• Bit 2 – CH0EN: DAC Channel 0 Output Enable
Setting this bit will make channel 0 available on pin unless IDOEN is set to 1.
• Bit 1 – LPMODE: DAC Low Power Mode
Setting this bit enables the DAC Low Power mode. The DAC is turned off between each conver-
sion to save current. Conversion time will be doubled if new conversions are started in this
mode.
• Bit 0 – ENABLE: DAC Enable
This bit enables the entire DAC.
• Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 6:5 – CHSEL[1:0]: DAC Channel Selection
These bits control what DAC channels that are enabled and operating.
available selections.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
R
7
–
0
7
–
R
0
R/W
R
6
–
0
6
0
CHSEL[1:0]
R/W
R
5
–
0
5
0
IDOEN
R/W
4
0
R
4
–
0
CH1EN
R/W
Atmel AVR XMEGA AU
3
0
R
3
–
0
CH0EN
R/W
2
0
R
2
–
0
LPMODE
CH1TRIG
R/W
R/W
1
0
1
0
Table 29-1
CH0TRIG
ENABLE
R/W
R/W
0
0
0
0
shows the
CTRLA
CTRLB
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