ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 254

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.14.3
8331A–AVR–07/11
CNTL – Endpoint Counter Low Byte
interrupts or software intervention. See
packet transfer.
• Bit 4 – PINGPONG: Ping-Pong Enable
Setting this bit enables ping-pong operation. Ping-pong operation enables both endpoints (IN
and OUT) with same address to be used in the same direction to allow double buffering and
maximize throughput. The endpoint in the opposite direction must be disabled when ping-pong
operation is enabled. Ping-pong operation is not possible for control endpoints. See
Operation” on page 239
• Bit 3 – INTDSBL: Interrupt Disable
Setting this bit disables all enabled interrupts from the endpoint hence only the interrupt flags in
the STATUS register are updated when interrupt conditions occur. The FIFO does not store this
endpoint configuration table address upon transaction complete for the endpoint when interrupts
are disabled for an endpoint. Clearing this bit, enables all previously enables interrupts again.
• Bit 2 – STALL: Endpoint STALL
This bit controls the STALL behavior if the endpoint.
• Bit 1:0 – BUFSIZE[1:0]: Data Size
These bits configure the maximum data payload size for the endpoint. Incoming data bytes
exceeding the maximum data payload size are discarded.
• Bit 2:0 – BUFSIZE[2:0]: Data Size
These bits configure the maximum data payload size for the endpoint when configured for iso-
chronous operation.
Table 20-5.
Note:
The CNTL and CNTH registers represent the 10-bit value CNT that contains number of bytes
received in the last OUT or SETUP transaction for an OUT endpoint, or of the number of bytes to
be sent in the next IN transaction for an INt endpoint.
BUFSIZE[2:0]
100
101
110
111
000
001
010
011
1. Setting only available for isochronous endpoints
(1)
(1)
(1)
(1)
BUFSIZE configuration
Group Configuration
for details.
1023
128
256
512
16
32
64
8
”Multi-packet transfers” on page 240
Description
8 bytes buffer size
16 bytes buffer size
32 bytes buffer size
64 bytes buffer size
128 bytes buffer size
256 bytes buffer size
512 bytes buffer size
1023 bytes buffer size
Atmel AVR XMEGA AU
for details on multi-
”Ping-Pong
254