ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 428

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.3
33.4
33.4.1
33.4.2
33.4.3
33.4.4
33.5
8331A–AVR–07/11
NVM Controller
NVM Commands
NVM Controller Busy Status
Action Triggered Commands
NVM Read Triggered commands
NVM Write Triggered Commands
Write/Execute Protection
The device can be locked to prevent read and/or write of the NVM. There are separate lock bits
for external programming access, and self-programming access to the Boot Loader Section,
Application Section and Application Table Section.
Access to the Non Volatile Memories is done through the NVM Controller. This controls NVM
timing and access privileges, and holds the status of the NVM. This is the common NVM inter-
face for both external programming and self-programming. For more details refer to
Description” on page
The NVM Controller has a set of commands used to perform task on the NVM. This is done by
writing the selected command to the NVM Command Register. In addition, data and addresses
must be read/written from/to the NVM Data and Address registers for memory read/write
operations.
When a selected command is loaded and address and data is setup for the operation, each
command has a trigger that will start the operation. Based on these triggers, there are three
main types of commands.
Action triggered commands are triggered when the Command Execute (CMDEX) bit in the NVM
Control Register A (CTRLA) is written. Action triggered commands typically are used for opera-
tions which do not read or write the NVM, such as the CRC check.
NVM read triggered commands are triggered when the NVM is read, and this is typically used for
NVM read operations.
NVM Write Triggered commands are triggered when the NVM is written, and this is typically
used for NVM write operations.
Most command triggers are protected from accidental modification/execution during self-pro-
gramming. This is done using the Configuration Change Protection (CCP) feature which
requires a special write or execute sequence in order to change a bit or execute an instruction.
For details on the CCP, refer to
When the NVM Controller is busy performing an operation, the Busy flag in the NVM Status
Register is set and the following registers are blocked for write access:
• NVM Command Register
• NVM Control A Register
• NVM Control B Register
• NVM Address registers
• NVM Data registers
448.
”Configuration Change Protection” on page 12
Atmel AVR XMEGA AU
”Register
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