ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet
ATxmega32D4
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ATxmega32D4 Summary of contents
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This document contains complete and detailed description of all modules included in TM the AVR® XMEGA D Microcontroller family. The XMEGA family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR ...
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About the Manual This document contains in-depth documentation of all peripherals and modules available for the AVR XMEGA D Microcontroller family. All features are documented on a functional level and described in a general sense. All peripherals and modules ...
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Overview The XMEGA family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instruc- tions in a single clock cycle, the XMEGA D achieves ...
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Block Diagram Figure 2-1. XMEGA D Block Diagram PA[0..7] PORT A (8) ACA ADCA AREFA VCC/10 Int. Refs. Tempref AREFB PB[0..7] PORT B (8) IRCOM 8210B–AVR–04/10 PR[0..1] PQ[0..3] XTAL1 TOSC1 XTAL2 TOSC2 Oscillator Circuits/ Clock Generation EVENT ROUTING NETWORK ...
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AVR CPU 3.1 Features • 8/16-bit high performance AVR RISC CPU – 138 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack Pointer accessible in I/O memory space • Direct ...
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Figure 3-1. The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated ...
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The Program Memory is divided in two sections, the Application Program section and the Boot Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that is used for self-programming of the Application Flash ...
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A flexible interrupt controller has dedicated control registers with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate interrupt vector, starting from the Reset Vector at address 0 in the Program Memory. All interrupts ...
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Status Register The Status Register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status ...
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Figure 3-4. Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. The Register File is located in a separate address space, so the registers are not ...
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RAMP and Extended Indirect Registers In order to access program memory or data memory above 64K bytes, the address or address pointer must be more than 16-bits. This is done by concatenating one register to one of the X-, ...
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Accessing 16-bits Registers The AVR data bus is 8-bit so accessing 16-bit registers requires atomic operations. These regis- ters must be byte-accessed using two read or write operations. Due to this each 16-bit register uses an 8-bit register for ...
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Sequence for execution of protected SPM/LPM 1. The application code writes the signature for execution of protected SPM/LPM to the CCP register. 2. Within 4 instruction cycles, the application code must execute the appropriate instruc- tion. The protected change ...
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RAMPD - Extended Direct Addressing Register This register is concatenated with the operand for direct addressing (LDS/STS) of the whole data memory space on devices with more than 64K bytes of data memory. When accessing data addresses below 64K ...
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RAMPZ - Extended Z-Pointer Register This register is concatenated with the Z-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory space on devices with more than 64K bytes of data memory. RAMPZ is concatenated with the Z-register when ...
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Bit +0x0D Read/Write Initial Value Note: • Bit 7:0 - SP[7:0]: Stack Pointer Register Low byte These bits hold the 8 LSB of the 16-bits Stack Pointer (SP). 3.14.8 SPH - Stack Pointer Register High Bit +0x0E Read/Write Initial Value ...
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Bit 4 – S: Sign Bit The Sign bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit ...
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Memories 4.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section ...
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All AVR instructions are bits wide, and each Flash location is 16 bits wide. The Flash memory in XMEGA is organized in two main sections, the Application Section and the Boot Loader section, as shown in but ...
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Application Section and the Application Table Section enable safe parameter storage in the Program Memory. If this section is not used for data, appli- cation code can be reside here. 4.3.3 Boot Loader Section ...
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Data Memory The Data memory contains the I/O Memory, internal SRAM, optionally memory mapped EEPROM and external memory if available. The data memory is organized as one continuous memory section, as shown in Figure 4-2. I/O Memory, EEPROM and ...
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OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. In the address range 0x00 - 0x1F, specific bit manipulating and checking instructions are available. The I/O memory definition for an XMEGA device is shown in ...
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ADDR1 - Non-Volatile Memory Address Register 1 Bit +0x01 Read/Write Initial Value • Bit 7:0 - ADDR[15:8]: NVM Address Register Byte 1 This register gives the address high byte when accessing either of the memory locations. 4.12.3 ADDR0 - ...
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DATA0 - Non-Volatile Memory Data Register 0 Bit +0x04 Read/Write Initial Value • Bit 7:0 - DATA[7:0]: NVM Data Register Byte 0 This register gives the data value byte 0 when accessing either of the memory locations. 4.12.7 CMD ...
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CTRLB - Non-Volatile Memory Control Register B Bit +0x0C Read/Write Initial Value • Bit 7:4 - Reserveds These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this ...
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Bit 3:2 - SPMLVL[1:0]: SPM Ready Interrupt Level These bits enable the Interrupt and select the interrupt level as described in grammable Multi-level Interrupt Controller” on page will be triggered when the BUSY flag in the STATUS is set ...
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Bit 0 - FLOAD: Flash Page Buffer Active Loading The FLOAD flag indicates that the temporary Flash page buffer has been loaded with one or more data bytes. Immediately after a Flash load command has been issues and byte ...
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Register Description – Fuses and Lockbit 4.13.1 FUSEBYTE1 - Non-Volatile Memory Fuse Byte1 - Watchdog Configuration Bit +0x01 Read/Write Initial Value • Bit 7:4 - WDWPER[3:0]: Watchdog Window Timeout Period The WDWPER fuse bits are used to set initial ...
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Bit 1:0 - BODPD[1:0]: BOD operation in power-down mode The BODPD fuse bits set the BOD operation mode in all sleep modes except Idle mode. For details on the BOD and BOD operation modes refer to Table 4-2. BODPD[1:0] ...
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Table 4-4. WDLOCK • Bit 0 - Reserved This fuse bit is reserved. For compatibility with future devices, always write this bit to one when this register is written. 4.13.4 FUSEBYTE5 - Non-Volatile Memory Fuse Byte 5 Bit +0x05 Read/Write ...
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Changing of the EESAVE fuse bit takes effect immediately after the write time-out elapses. Hence possible to update EESAVE and perform a chip erase according to the new setting of EESAVE without leaving and re-entering programming mode • ...
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Table 4-8. BLBB[1:0] • Bit 5:4 - BLBA[1:0]: Boot Lock Bit Application Section These bits indicate the locking mode for the Application Section. Even though the BLBA bits are writable, they can only be written to a stricter locking. Resetting ...
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Bit 3:2 - BLBAT[1:0]: Boot Lock Bit Application Table Section These bits indicate the locking mode for the Application Table Section. Even though the BLBAT bits are writable, they can only be written to a stricter locking. Resetting the ...
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Register Description - Production Signature Row 4.14.1 RCOSC2M - Internal 2 MHz Oscillator Calibration Register Bit +0x00 Read/Write Initial Value • Bit 7:0 - RCOSC2M[7:0]: Internal 2 MHz Oscillator Calibration Value This byte contains the oscillator calibration value for ...
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LOTNUM0 - Lot Number Register 0 LOTNUM0, LOTNUM1, LOTNUM2, LOTNUM3, LOTNUM4 and LOTNUM5 contains the LOT number for each device. Together with the wafer number and wafer coordinates this gives an unique identifier or serial number for the device. ...
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LOTNUM4 - Lot Number Register 4 Bit +0x0C Read/Write Initial Value • Bit 7:0 - LOTNUM4[7:0] - LOT Number Byte 4 This byte contains byte 4 of the LOT number for the device. 4.14.9 LOTNUM5 - Lot Number Register ...
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COORDX1 - Wafer Coordinate X Register 1 Bit +0x13 Read/Write Initial Value • Bit 7:0 - COORDX0[7:0] - Wafer Coordinate X Byte 1 This byte contains byte 1 of wafer coordinate X for the device. 4.14.13 COORDY0 - Wafer ...
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ADCACAL1 - ADCA Calibration Register 1 Bit +0x21 Read/Write Initial Value • Bit 7:0 - ADCACAL1[7:0] - ADCA Calibration Byte 1 This byte contains byte 1 of the ADCA calibration data, and must be loaded into the ADCA CALH ...
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Register Description – MCU Control 4.16.1 DEVID0 - MCU Device ID Register 0 The DEVID0, DEVID1 and DEVID2 contains the 3-byte identification that identify each micro- controller device type. For details on the actual ID refer to the device ...
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MCUCR – MCU Control Register Bit +0x06 Read/Write Initial Value • Bit 7:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is ...
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Register Summary - NVM Controller Address Name Bit 7 +0x00 ADDR0 +0x01 ADDR1 +0x02 ADDR2 +0x03 Reserved – +0x04 DATA0 +0x05 DATA1 +0x06 DATA2 +0x07 Reserved – +0x08 Reserved – +0x09 Reserved – +0x0A CMD – +0x0B CTRLA – ...
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Register Summary - Production Signature Row Address Auto Load Name +0x00 YES RCOSC2M +0x01 Reserved +0x02 YES RCOSC32K +0x03 YES RCOSC32M +0x04 Reserved +0x05 Reserved +0x06 Reserved +0x07 Reserved +0x08 NO LOTNUM0 +0x09 NO LOTNUM1 +0x0A NO LOTNUM2 +0x0B ...
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Register Summary - General Purpose I/O Registers Address Name Bit 7 +0x00 GPIOR0 +0x01 GPIOR1 +0x02 GPIOR2 +0x03 GPIOR3 4.21 Register Summary - MCU Control Address Name Bit 7 +0x00 DEVID0 +0x01 DEVID1 +0x02 DEVID2 +0x03 REVID – +0x05 ...
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Event System 5.1 Features • Inter peripheral communication and signalling • CPU independent operation • 4 Event Channels allows for signals to be routed at the same time • 100% predictable timing between peripherals • Events ...
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Figure 5-1. The CPU is not part of the Event System, but it indicates that it is possible to manually generate events from software or by using the on-chip debug system. The Event System works in active and idle mode. ...
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Events can be manually generated by writing to the STROBE and DATA registers. 5.3.1 Signaling Events Signaling events are the most basic type of events. A signaling event does not contain any infor- mation apart from the indication of a ...
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Figure 5-3. Having four multiplexers means that it is possible to route up to four events at the same time also possible to route one event through several multiplexers. Not all XMEGA parts contain all peripherals. This only ...
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It takes maximum two clock cycles from an event is generated until the event actions in other peripherals is triggered. It takes one clock ...
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Figure 5-4 QDPH90 are the two quadrature signals. When QDPH90 leads QDPH0, the rotation is defined as positive or forward. When QDPH0 leads QDPH90, the rotation is defined as negative, or reverse. The concatenation of the two phase signals is ...
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Register Description 5.8.1 CHnMUX – Event Channel n Multiplexer Register . Bit Read/Write Initial Value • Bit 7:0 - CHnMUX[7:0]: Channel Multiplexer These bits select the event source according to devices regardless of if the peripheral is present or ...
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Table 5-3. CHnMUX[7:4] 0111 0111 1000 1001 1010 1011 1100 1100 1101 1101 1110 1110 1111 1111 Note: Table 5-4. T/C Event 5.8.2 CHnCTRL – Event Channel n Control Register . Bit ...
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Bit 6:5 - QDIRM[1:0]: Quadrature Decode Index Recognition Mode These bits determine the quadrature state for the QDPH0 and QDPH90 signals where a valid index signal is recognized and the counter index data event is given according to page ...
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STROBE – Event Strobe Register A single event lasting for one peripheral clock cycle will be generated. Bit +0x10 Read/Write Initial Value • Bit 7:4 - Reserved These bits are reserved and will always be read as zero. For ...
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Register Summary Address Name Bit 7 +0x00 CH0MUX +0x01 CH1MUX +0x02 CH2MUX +0x03 CH3MUX +0x04 +0x05 +0x06 +0x07 +0x08 CH0CTRL – +0x09 CH1CTRL – +0x0A CH2CTRL – +0x0B CH3CTRL – +0x0C +0x0D +0x0E +0x0F +0x10 STROBE – +0x11 DATA ...
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System Clock and Clock options 6.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator ...
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Figure 6-1. Brown-out Detection 6.3 Clock Distribution Figure 6-1 on page 56 6.3.1 System Clock - clk SYS The System Clock is the output from the main system clock selection. This is fed into the pres- calers that are used ...
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Peripheral Clock - clk The majority of peripherals and system modules use the Peripheral Clock. This includes the Event System, Interrupt Controller and RAM. This clock is always synchronous to the CPU Clock but may run even if the ...
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MHz Run-time Calibrated Internal Oscillator This RC oscillator provides an approximate 2 MHz clock. The oscillator employs a Digital Fre- quency Looked Loop (DFLL) that can be enabled for automatic run-time calibration of the oscillator. A factory-calibrated value ...
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System Clock, RTC and as the DFLL reference. Figure 6-4. Two capacitors, C1 and C2, may be added to match the required load capacitance for the con- nected ...
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The System Clock selection and prescaler registers are protected by the Configuration Change Protection mechanism, employing a timed write procedure for changing the system clock and prescaler settings. For details refer to 6.6 PLL with 1-31x Multiplication Factor A built-in ...
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Figure 6-6. TOSC1 TOSC2 When the DFLL is enabled it will count each oscillator clock cycle, and for each reference clock edge, the counter value is compared to the fixed ideal relationship between the reference clock and the 1.024 kHz ...
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System Clock (i.e clock reference for the PLL when this is used as the active system clock) and an clock or oscillator fails (stops), the device will: • Switch to the 2 ...
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Register Description - Clock 6.9.1 CTRL - System Clock Control Register Bit +0x00 Read/Write Initial Value • Bit 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits ...
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Bit 6:2 - PSADIV[4:0]: Prescaler A Division Factor These bits define the division ratio of the clock prescaler A according to can be written run-time to change the clock frequency of the clk clock, clk Table 6-2. PSADIV[4:0] • ...
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LOCK - Clock System Lock Register Bit +0x02 Read/Write Initial Value • Bit 7:1 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when ...
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Bit 0 - RTCEN: RTC Clock Source Enable Setting the RTCEN bit enables the selected clock source for the Real Time Counter. 6.10 Register Description - Oscillator 6.10.1 CTRL - Oscillator Control Register Bit +0x00 Read/Write Initial Value • ...
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STATUS - Oscillator Status Register Bit +0x01 Read/Write Initial Value • Bit 7:5 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this ...
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Table 6-5. FRQRANGE[1:0] • Bit 5 - X32KLPM: Crystal Oscillator 32.768 kHz Low Power Mode Setting this bit enables low power mode for the 32.768 kHz Crystal Oscillator. This will reduce the swing on the TOSC2 pin to save power. ...
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Bit 7:2 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 1 - XOSCFDIF: Failure Detection Interrupt ...
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Table 6-7. CLKSRC[1:0] Notes: • Bit 5 - Reserved This bit is reserved and will always be read as zero. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 4:0 - ...
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Register Description - DFLL32M/DFLL2M 6.11.1 CTRL - DFLL Control Register Bit +0x00 Read/Write Initial Value • Bit 7:1 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these ...
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Bit 4:0 - CALH[12:8]: DFLL Calibration bits These bits hold the 6 Most Significant Bits (MSB) of the calibration value for the oscillator. A fac- tory-calibrated value is loaded from the signature row of the device and written to ...
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Register Summary - Clock Address Name Bit 7 +0x00 CTRL – +0x01 PSCTRL – +0x02 LOCK – +0x03 RTCCTRL – +0x04 Reserved – +0x05 Reserved – +0x06 Reserved – +0x07 Reserved – 6.13 Register Summary - Oscillator Address Name ...
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Power Management and Sleep 7.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction register to disable clock to unused peripherals 7.2 Overview XMEGA provides various sleep modes and ...
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Table 7-1 on page 75 and wake-up sources. Table 7-1. Sleep modes Idle Power-down Power-save Standby Extended Standby The wake-up time for the device is dependent on the sleep mode and the main clock source. The start-up time for the ...
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Standby Mode Standby mode is identical to Power-down with the exception that the enabled system clock sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces the wake-up time. 7.3.5 Extended Standby Mode Extended ...
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Table 7-2. SMODE[2:0] • Bit 1 - SEN: Sleep Enable This bit must be set to make the MCU enter the selected sleep mode when the SLEEP instruc- tion is executed. To avoid unintentional entering of sleep modes ...
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Bit 7:2 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 1 - ADC: Power Reduction ADC ...
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Bit 0 - TC0: Timer/Counter 0 Setting this bit stops the clock to the Timer/Counter 0. When the bit is cleared the peripheral will continue like before the shut down. 7.7 Register Summary - Sleep Address Name Bit 7 ...
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Reset System 8.1 Features • Power-on reset source • Brown-out reset source • Software reset source • External reset source • Watchdog reset source • Program and Debug Interface reset source 8.2 Overview The Reset System will issue a ...
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Figure 8-1. 8210B–AVR–04/10 Reset system overview Reset Status Register Power - On Detection Reset Brown - Out Detection Reset External Reset Program and Debug Interface Reset Watchdog Reset Software Reset XMEGA D Reset Delay Counter Oscillator Startup Oscillator Calibration Counter ...
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Reset Sequence Reset request from any reset source immediately reset the device, and keep it in reset as long as the request is active. When all reset requests are released, the device will go through three stages before the ...
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The Brown-out detection (BOD) must be enabled to ensure safe operation and detect if V Only the Power-on reset Flag will be set after Power-on reset. The Brown-out Reset Flag is not set ...
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Brown-Out Detection The Brown-Out Detection (BOD) circuit monitors that the V trigger level, V low the trigger level for a minimum time, t above the trigger level again. Figure 8-4. For characterization data programmable BODLEVEL ...
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Sampled: In this mode the BOD circuit will sample the VCC level with a period identical to the 1 kHz output from the Ultra Low Power (ULP) oscillator. Between each sample the BOD is turned off. This mode will ...
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Figure 8-6. For information on configuration and use of the WDT, refer to the page 89. 8.4.5 Software reset The Software reset makes it possible to issue a system reset from software by writing to the Software Reset bit in ...
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Register Description 8.5.1 STATUS - Reset Status Register Bit +0x00 Read/Write Initial Value • Bit 7:6 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to ...
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Bit 0 - SWRST: Software Reset When this bit is set, a Software reset will occur. The bit is cleared when a reset is issued. This bit is protected by the Configuration Change Protection, for details refer to Protection” ...
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WDT – Watchdog Timer 9.1 Features • 11 selectable timeout period, from • Two operation modes – Standard mode – Window mode • Runs from 1 kHz Ultra Low Power clock reference • Configuration lock ...
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Window Mode Operation In window mode operation the WDT uses two different timeout periods, a "closed" window time- out period (TO defines a duration from where the WDT cannot be reset: if the WDT is ...
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Registers Description 9.7.1 CTRL – Watchdog Timer Control Register Bit +0x00 Read/Write (unlocked) Read/Write (locked) Initial Value (x = fuse) • Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, ...
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Bit 1 - ENABLE: Watchdog Enable This bit enables the WDT. In order to change this bit the CEN bit in must be written to one at the same time. This bit is protected by the Configuration Change Pro- ...
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Table 9-2. WPER[3:0] 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 • Bit 1 - WEN: Watchdog Window Mode Enable This bit enables the Watchdog Window Mode. In order to change this bit the WCEN bit in ”WINCTRL ...
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Register Summary Address Name Bit 7 +0x00 CTRL – +0x01 WINCTRL – +0x02 STATUS – 8210B–AVR–04/10 Bit 6 Bit 5 Bit 4 Bit 3 – PER[3:0] – WPER[3:0] – – – XMEGA D Bit 2 Bit 1 Bit 0 ...
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Interrupts and Programmable Multi-level Interrupt Controller 10.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts ...
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The RET (subroutine return) instruction cannot be used when returning from the inter- rupt handler routine, as this will not return the PMIC to its right state. 10.4 Interrupts All interrupts and the reset vector each have a separate ...
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A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the program counter is popped from the stack and the stack pointer is incremented. 10.5 Interrupt level The interrupt level is independently selected for ...
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Figure 10-1. Static priority. 10.6.2 Round-robin scheduling To avoid the possible starvation problem for low level interrupts with static priority, the PMIC gives the possibility for round-robin scheduling for low level interrupts. When round-robin sched- uling is enabled, the interrupt ...
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Moving Interrupts Between Application and Boot Section The interrupt vectors can be moved from the default location in the Application Section in Flash to the start of the Boot Section. 10.8 Register Description 10.8.1 STATUS - PMIC Status Register ...
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This register is not reinitialized to its initial value if round-robing scheduling is disabled default static priority is needed the register must be written to zero. 10.8.3 CTRL - PMIC Control Register Bit +0x02 ...
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I/O Ports 11.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events • Asynchronous wake-up signalling • ...
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Figure 11-1. General I/O pin functionality. 11.3 Using the I/O Pin Use of an I/O pin is controlled from the user software. Each port has one Data Direction (DIR), Data Output Value (OUT) that is used for port pin control. ...
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I/O Pin Configuration The Pin n Configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin can be set in a totem-pole, wired-AND, or wired-OR configuration also possible to enable inverted input and output for ...
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Pull-up Figure 11-4. I/O pin configuration - Totem-pole with pull-up (on input). 11.4.4 Bus-keeper The bus-keeper’s week output produces the same logical level as the last output level. It acts as a pull-up if the last level was '1', ...
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Wired-OR Figure 11-6. Output configuration - Wired-OR with optional pull-down. 11.4.6 Wired-AND Figure 11-7. Output configuration - Wired-AND with optional pull-up. 11.5 Reading the Pin value Independent of the pin data direction, the pin value can be read from ...
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Figure 11-8. Synchronization when reading an externally applied pin value. 11.6 Input Sense Configuration Input sensing is used to detect an edge or level on the I/O pin input. The different sense configu- rations that are available for each pin ...
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Port Interrupt Each port has two interrupt vectors, and it is configurable which pins on the port that can be used to trigger each interrupt request. Port interrupts must be enabled before they can be used. Which sense configurations ...
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Table 11-3. Sense settings Rising edge Falling edge Both edges Low level 11.8 Port Event Port pins can generate an event when there is a change on the pin. The sense configurations decide when each pin will generate events. Event ...
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Figure 11-10. Port override signals and related logic 11.10 Clock and Event Output It is possible to output both the Peripheral Clock and the signaling event from Event Channel 0 to pin. Output port pin is selected from software. If ...
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Virtual Registers Virtual port registers allows for port registers in the extended I/O memory space to be mapped virtually in the I/O memory space. When mapping a port, writing to the virtual port register will be the same as ...
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DIRTGL - Data Direction Toggle Register Bit +0x03 Read/Write Initial Value • Bit 7:0 - DIRTGL[7:0]: Port Data Direction Toggle This register can be used instead of a Read-Modify-Write to toggle the direction on individual pins. Writing a one ...
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Bit 7:0 - OUTCLR[7:0]: Data Output Value Clear This register can be used instead of a Read-Modify-Write to set the output value on individual pins to zero. Writing a one to a bit will clear the corresponding bit in ...
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INT0MASK - Interrupt 0 Mask Register Bit +0x0A Read/Write Initial Value • Bit 7:0 - INT0MSK[7:0]: Interrupt 0 Mask Register These bits are used to mask which pins can be used as sources for port interrupt 0. If INT0MASKn ...
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PINnCTRL - Pin n Configuration Register Bit Read/Write Initial Value • Bit 7 - Reserved This bit is reserved and will always be read as zero. For compatibility with future devices, always write this bit to zero when this ...
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Table 11-5. ISC[2:0] 101 110 111 Note: 11.14 Register Description – Multiport Configuration 11.14.1 MPCMASK - Multi-pin Configuration Mask Register Bit +0x00 Read/Write Initial Value • Bit 7:0 - MPCMASK[7:0]: Multi-pin Configuration Mask The MPCMASK register enables several pins in ...
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VPCTRLB - Virtual Port-map Control Register B Bit +0x03 Read/Write Initial Value • Bit 7:4 - VP3MAP: Virtual Port 3 Mapping These bits decide which ports should be mapped to Virtual Port 3. The registers DIR, OUT, IN and ...
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Bit 7:6 - Reserved These bits are reserved and will always be read as one. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 5:4 - EVOUT[1:0] - Event Output ...
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Register Description – Virtual Port 11.15.1 DIR - Data Direction Bit +0x00 Read/Write Initial Value • Bit 7:0 - DIR[7:0]: Data Direction Register This register sets the data direction for the individual pins in the port mapped by "VPCTRLA ...
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INTFLAGS - Interrupt Flag Register Bit +0x03 Read/Write Initial Value • Bit 7:2 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this ...
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Register Summary – Ports Address Name Bit 7 +0x00 DIR +0x01 DIRSET +0x02 DIRCLR +0x03 DIRTGL +0x04 OUT +0x05 OUTSET +0x06 OUTCLR +0x07 OUTTGL +0x08 IN +0x09 INTCTRL – +0x0A INT0MASK +0x0B INT1MASK +0x0C INTFLAGS – +0x0D Reserved – ...
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TC - 16-bit Timer/Counter 12.1 Features • 16-bit Timer/Counter • Double Buffered Timer Period Setting • Combined Compare or Capture (CC) Channels ( and D) • All Compare or Capture Channels are Double Buffered ...
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Figure 12-1. 16-bit Timer/Counter and Closely Related Peripheral Timer/Counter Base Counter Timer Period Compare/Capture Channel B Compare/Capture Channel A Comparator The Timer/Counter consists of a Base Counter and a set of Compare or Capture (CC) channels. The Base Counter can ...
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Definitions The following definitions are used extensively throughout the Timer/Counter documentation: Table 12-1. Name BOTTOM MAX TOP UPDATE In general the term Timer is used when the Timer/Counter clock control is handled by an internal source and the term ...
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Figure 12-2. Timer/Counter Block Diagram Bus Bridge The Counter Register (CNT), the Period Registers w/buffer (PER and PERBUF), and the com- pare and Capture registers w/buffers (CCx and CCxBUF) are 16-bit registers. During normal operation the counter value is continuously ...
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Clock and Event Sources The Timer/Counter can be clocked from the Peripheral Clock (clk tem, and Figure 12-3. Clock and Event Selection clk The Peripheral Clock is fed into the Common Prescaler (common for all Timer/Counters in a device). ...
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Figure 12-4. Period and Compare Double Buffering When the CC channels is used for capture operation a similar Double buffering mechanism is used, but the Buffer Valid flag is set on the capture event as shown in the buffer and ...
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Counter Operation Dependent of the mode of operation, the Counter is cleared, reloaded, incremented, or decre- mented at each Timer/Counter clock input. 12.6.1 Normal Operation In Normal Operation the Counter will count in the direction set by the Direction ...
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Figure 12-7. Changing The Period without Buffering CNT When double buffering is used, the buffer can be written at any time, but the Period Register is always updated on the “update” condition as shown in and generation of odd waveforms. ...
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Event Source Selection for capture operation The Event Action setting in the Timer/Counter will determine the type of capture that is done. The CC channel to use must be enabled individually before capture can be done. When the cap- ture ...
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Frequency Capture Selecting the frequency capture event action, makes the enabled capture channel perform a input capture and restart on any event. This enables Timer/Counter to use capture to measure the period or frequency of a signal directly. The ...
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Figure 12-11. Pulse-width capture of external signal. external signal events CNT 12.7.4 32-bit Input Capture Two Timer/Counters can be used together to enable true 32-bit Input Capture typical 32-bit Input Capture setup the overflow event of the least ...
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Waveform Generation The compare channels can be used for waveform generation on the corresponding port pins. To make the waveform visible on the connected port pin, the following requirements must be fulfilled waveform generation mode must be ...
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Figure 12-13. Single slope Pulse Width Modulation CNT WG Output The PER register defines the PWM resolution. The minimum resolution is 2-bit (PER=0x0003), and maximum resolution is 16-bit (PER=MAX). The following equation can be used for calculate the exact resolution ...
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Figure 12-14. Dual-slope Pulse Width Modulation CNT WG Output Using dual-slope PWM result in a lower maximum operation frequency compared to the single- slope PWM operation. The period register (PER) defines the PWM resolution. The minimum resolution is 2-bit (PER=0x0003), ...
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Figure 12-15. Port override for Timer/Counter 0 and 1 12.9 Interrupts and events The T/C can generate both interrupts and events. The Counter can generate an interrupt on overflow/underflow, and each CC channel has a separate interrupt that is used ...
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Timer/Counter Commands A set of commands can be given to the Timer/Counter by software to immediately change the state of the module. These commands give direct control of the Update, Restart, and Reset signals. An update command has the ...
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Register Description 12.11.1 CTRLA - Control Register A Bit +0x00 Read/Write Initial Value • Bit 7:4 - Reserved bits These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero ...
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Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode These bits ...
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CTRLD - Control Register D Bit +0x03 Read/Write Initial Value • Bit 7:5 – EVACT[2:0]: Event Action These bits define the Event Action the timer will perform on an event according to page 139. The EVSEL setting will decide ...
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Table 12-5. EVSEL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 12.11.5 CTRLE - Control Register E Bit +0x04 Read/Write Initial Value • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with ...
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Bit 3:2 - ERRINTLVL[1:0]:Timer Error Interrupt Level These bits enable the Timer Error Interrupt and select the interrupt level as described in rupts and Programmable Multi-level Interrupt Controller” on page • Bit 1:0 - OVFINTLVL[1:0]:Timer Overflow/Underflow Interrupt Level These ...
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Table 12-6. CMD • Bit 1 - LUPD: Lock Update: When this bit is set no update of the buffered registers is performed, even though an UPDATE condition has occurred. Locking the update ensures that all ...
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INTFLAGS - Interrupt Flag Register Bit +0x0C Read/Write Initial Value • Bit 7:4 - CCxIF: Compare or Capture Channel x Interrupt Flag The Compare or Capture Interrupt Flag (CCxIF) is set on a compare match input ...
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For more details refer to Bit +0x0F Read/Write Initial Value 12.11.12 CNTH - Counter Register H The CNTH and CNTL register pair represents the 16-bit value CNT. CNT contains the 16-bit counter value in the Timer/Counter. The CPU write access ...
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PERL - Period Register L Bit +0x26 Read/Write Initial Value • Bit 7:0 - PER[7:0] These bits holds the 8 LSB of the 16-bit Period register. 12.11.16 CCxH - Compare or Capture Register n H The CCxH and CCxL ...
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Bit +0x37 Read/Write Initial Value • Bit 7:0 - PERBUF[15:8] These bits holds the 8 MSB of the 16-bit Period Buffer register. 12.11.19 PERBUFL - Timer/Counter Period Buffer L Bit +0x36 Read/Write Initial Value • Bit 7:0 - PERBUF[7:0] These ...
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Register Summary Address Name Bit 7 +0x00 CTRLA – +0x01 CTRLB CCDEN +0x02 CTRLC – +0x03 CTRLD +0x04 CTRLE – +0x05 Reserved – +0x06 INTCTRLA – +0x07 INTCTRLB CCCINTLVL[1:0] +0x08 CTRLFCLR – +0x09 CTRLFSET – +0x0A CTRLGCLR – +0x0B ...
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Hi-Res - High Resolution Extension 13.1 Features • Increases Waveform Generator Resolution bits) • Supports Frequency generation, and single and dual-slope PWM operation • Supports Dead-Time Insertion (AWeX) • Supports Pattern Generation (AWeX) 13.2 Overview The ...
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Register Description 13.3.1 CTRLA - Hi-Res Control Register A Bit +0x00 Read/Write Initial Value • Bit 7:2 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits ...
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AWeX – Advanced Waveform Extension 14.1 Features • 4 Dead-Time Insertion (DTI) Units (8-pin) – 8-bit Resolution – Separate High and Low Side Dead-Time Setting – Double Buffered Dead-Time – Halts Timer During Dead-Time (Optional) • Event Controlled Fault ...
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The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the waveform generator output from the Compare Channel A can be distributed to and override all the port ...
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Figure 14-2. Timer/Counter extensions and port override logic 8210B–AVR–04/ hannel hannel W G ...
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Dead Time Insertion The Dead Time Insertion (DTI) unit enables generation of “off” time where both the non-inverted Low Side (LS) and inverted High Side (HS) of the WG output is low. This “off” time is called dead-time, and ...
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Figure 14-4. Dead Time Generator timing diagram "dti_cnt" "WG output" "dtls" "dths" 14.5 Pattern Generation The pattern generator extension reuses the DTI registers to produce a synchronized bit pattern on the port it is connected to. In addition, the waveform ...
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Fault Protection The Fault Protection feature enables fast and deterministic action when a fault is detected. The fault protection is event controlled, thus any event from the Event System can be used to trigger a fault action. When the ...
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Lock Register. For more details refer to Advanced Waveform Extension Lock Register” on page When the lock bit is set, the Control Register A, the Output Override Enable Register and the Fault Dedec.tion Event Mask register cannot be changed. To ...
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FDEMASK - Fault Detect Event Mask Register Bit +0x02 Read/Write Initial Value • Bit 7:0 - FDEVMASK[7:0]: Fault Detect Event Mask These bits enables the corresponding event channel as fault condition input source. Event from all event channels will ...
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Table 14-1. FDACT[1:0] 14.7.4 STATUS - Status Register Bit +0x04 Read/Write Initial Value • Bit 7:3 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero ...
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Bit 7:0 - DTBOTH: Dead-Time Both Sides Writing to this register will update both DTHS and DTLS registers at the same time (i.e. at the same I/O write access). 14.7.6 DTBOTHBUF - Dead-time Concurrent Write to Both Sides Buffer ...
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DTHSBUF - Dead-Time High Side Buffer Register Bit +0x0B Read/Write Initial Value • Bit 7:0 - DTHSBUF: Dead-Time High Side Buffer This register is the buffer for the DTHS Register. If double buffering is used, valid contents in this ...
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Register Summary Address Name Bit 7 +0x00 CTRL – +0x01 Reserved – +0x02 FDEMASK +0x03 FDCTRL – +0x04 STATUS – +0x05 Reserved – +0x06 DTBOTH +0x07 DTBOTHBUF +0x08 DTLS +0x09 DTHS +0x0A DTLSBUF +0x0B DTHSBUF +0x0C OUTOVEN 8210B–AVR–04/10 Bit ...
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RTC - Real Time Counter 15.1 Features • 16-bit resolution • Selectable clock reference – 32.768 kHz – 1.024 kHz • Programmable prescaler • 1 Compare register • 1 Period register • Clear Timer on overflow • Optional Interrupt/ ...
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Clock domains The RTC is asynchronous, meaning it operates from a different clock source and independently of the main System Clock and its derivative clocks such as the Peripheral Clock. For Control and Count register updates it will take ...
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STATUS - Real Time Counter Status Register Bit +0x01 Read/Write Initial Value • Bits 7:1 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero ...
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INTFLAGS - RTC Interrupt Flag Register Bit +0x03 Read/Write Initial Value • Bits 7:2 - Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when ...
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Bits 7:0 - CNT[15:8]: Real Time Counter value High byte These bits hold the 8 MSB of the 16-bit Real Time Counter value. 15.3.7 CNTL - Real Time Counter Register L Bit +0x08 Read/Write Initial Value • Bits 7:0 ...
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COMPH - Real Time Counter Compare Register H The COMPH and COMPL register pair represent the 16-bit value COMP. COMP is constantly compared with the counter value (CNT). A compare match will set the COMPIF in the INT- FLAGS ...
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Register Summary Address Name Bit 7 +0x00 CTRL – +0x01 STATUS – +0x02 INTCTRL – +0x03 INTFLAGS – +0x04 TEMP +0x08 CNTL +0x09 CNTH +0x0A PERL +0x0B PERH +0x0C COMPL +0x0D COMPH 15.5 Interrupt Vector Summary Table 15-2. RTC ...
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TWI – Two Wire Interface 16.1 Features • Fully Independent Master and Slave Operation • Multi-Master, Single Master, or Slave Only Operation • Phillips I • SMBus compatible • 100 kHz and 400 kHz support at low system clock ...
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It is possible to disable the internal TWI drivers in the device, and enabling a 4-wire interface for connecting external bus drivers. 16.3 General TWI Bus Concepts The Two-Wire Interface (TWI) provides a simple two-wire bi-directional bus consisting of a ...
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Figure 16-2. Basic TWI Transaction Diagram Topology SDA SCL The master provides the clock signal for the transaction, but a device connected to the bus is allowed to stretch the low level period of the clock to decrease the clock ...
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Bit Transfer As illustrated by period of the SCL line. Consequently the SDA value can only be changed during the low period of the clock. This is ensured in hardware by the TWI module. Figure 16-4. Data Validity SDA ...
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Figure 16-5. Master Write Transaction S Given that the slave acknowledges the address, the master can start transmitting data (DATA) and the slave will ACK or NACK (A/A) each byte data packets are to be transmitted, the master ...
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Clock and Clock Stretching All devices connected to the bus are allowed to stretch the low period of the clock to slow down the overall clock frequency or to insert wait states while processing data. A device that needs ...
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Figure 16-9. TWI Arbitration Figure 16-9 devices are able to issue a START condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while DEVICE2 is transmitting a low level. Arbitration between a repeated START condition ...
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The result of this is that the device with the shortest clock period determines the high period while the low ...
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If a START condition is generated internally while in idle state the owner state is entered. If the complete transaction was performed without interference, i.e. no collisions are detected, the master will issue a STOP condition and the bus state ...
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Transmitting Address Packets After issuing a START condition, the master starts performing a bus transaction when the mas- ter Address register is written with the slave address and direction bit. If the bus is busy the TWI master will ...
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If a collision is detected the master looses arbitration and the Arbitration Lost flag is set. 16.6 TWI Slave Operation The TWI slave is byte-oriented with optional interrupts after each byte. There ...
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The R/W Direction flag reflects the direction bit received with the address. This can be read by software to determine the type of operation currently in progress. Depending on the R/W direction bit and bus condition one of four distinct ...
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Register Description - TWI 16.8.1 CTRL– TWI Common Control Register Bit +0x00 Read/Write Initial Value • Bit 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to ...
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Bit 4 - WIEN: Write Interrupt Enable Setting the Write Interrupt Enable (WIEN) bit enables the Write Interrupt when the Write Interrupt Flag (WIF) in the STATUS register is set. In addition the INTLVL bits must be unequal zero ...
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CTRLC - TWI Master Control Register C Bit +0x02 Read/Write Initial Value • Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this ...
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STATUS - Master Status Register Bit +0x03 Read/Write Initial Value • Bit 7 - RIF: Read Interrupt Flag This Read Interrupt Flag (RIF) is set when a byte is successfully received in Master Read mode, i.e. no arbitration lost ...
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Bit 2 - BUSERR: Bus Error The Bus Error (BUSERR) flag is set if an illegal bus condition has occurred. An illegal bus condi- tion occurs if a Repeated START or STOP condition is detected, and the number of ...
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ADDR - TWI Master Address Register Bit +0x05 Read/Write Initial Value When the Address (ADDR) register is written with a slave address and the R/W-bit while the bus is idle, a START condition is issued, and the 7-bit slave ...
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Register Description - TWI Slave 16.10.1 CTRLA - TWI Slave Control Register A Bit +0x00 Read/Write Initial Value • Bit 7:6 - INTLVL[1:0]: TWI Slave Interrupt Level The Slave Interrupt Level (INTLVL) bits select the interrupt level for the ...
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Bit 2 - ACKACT: Acknowledge Action The Acknowledge Action (ACKACT) bit defines the slave's acknowledge behavior after an address or data byte is received from the master. The Acknowledge Action is executed when a command is written to the ...
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Bit 7 - DIF: Data Interrupt Flag The Data Interrupt Flag (DIF) is set when a data byte is successfully received, i.e. no bus error or collision occurred during the operation. Writing a one to this bit location will ...
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Bit 0 - AP: Slave Address or Stop The Slave Address or Stop (AP) flag indicates whether a valid address or a STOP condition caused the last setting of the APIF in the STATUS register. Table 16-8. AP 16.10.4 ...
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ADDRMASK - TWI Slave Address Mask Register Bit +0x05 Read/Write Initial Value • Bit 7:1 - ADDRMASK[7:1]: Read/Write Direction These bits in the ADDRMASK register can act as a second address match register address mask register depending ...
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Register Summary - TWI Address Name Bit 7 +0x00 CTRL – +0x01 MASTER +0x08 SLAVE 16.12 Register Summary - TWI Master Address Name Bit 7 +0x00 CTRLA INTLVL[1:0] +0x01 CTRLB – +0x02 CTRLC – +0x03 STATUS RIF +0x04 BAUD ...
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SPI – Serial Peripheral Interface 17.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Eight Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
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In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of this clock signal, the minimum low and high periods must be: Low period: longer than 2 CPU clock cycles. ...
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As the SS pin is used to signal start and end of transfer also useful for doing packet/byte synchronization, keeping the Slave bit counter synchronous with the Master clock generator. 17.5 Data Modes There are four combinations of ...
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Register Description 17.6.1 CTRL - SPI Control Register Bit +0x00 Read/Write Initial Value • Bit 7 - CLK2X: SPI Clock Double When this bit is set the SPI speed (SCK Frequency) will be doubled in Master mode (see 17-4 ...
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The relationship between SCK and the Peripheral Clock frequency (clk 4 on page Table 17-4. 17.6.2 INTCTRL - SPI Interrupt Control Register Bit +0x01 Read/Write Initial Value • Bits 7:2 - Reserved These bits are unused and reserved for future ...
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Bit 6 - WRCOL: Write Collision Flag The WRCOL bit is set if the DATA register is written during a data transfer. The WRCOL bit is cleared by first reading the STATUS register with WRCOL set, and then accessing ...
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USART 18.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • Enhanced Baud Rate Generator • Supports Serial Frames with ...
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Figure 18-1. USART Block Diagram The Clock Generation logic has a fractional baud rate generator that is able to generate a wide range of USART baud rates. It also includes synchronization logic for external clock input in syn- chronous slave ...