ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 8
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
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123
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Quantity:
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Part Number:
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Manufacturer:
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1 910
Company:
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Part Number:
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Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
3.6
8210B–AVR–04/10
Instruction Execution Timing
A flexible interrupt controller has dedicated control registers with an additional Global Interrupt
Enable bit in the Status Register. All interrupts have a separate interrupt vector, starting from the
Reset Vector at address 0 in the Program Memory. All interrupts have a programmable interrupt
level. Within each level they have priority in accordance with their interrupt vector position where
the lower interrupt vector address has the higher priority.
The AVR CPU is driven by the CPU clock clk
on page 8
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 3-2.
Figure 3-3 on page 8
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 3-3.
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
ALU Operation Execute
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the parallel instruction fetches and instruction executions enabled by the Har-
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
shows the internal timing concept for the Register File. In a single clock
clk
clk
CPU
CPU
T1
T1
CPU
. No internal clock division is used.
T2
T2
T3
T3
XMEGA D
T4
T4
Figure 3-2
8