ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 235
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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20.12.2
8210B–AVR–04/10
CTRLB - ADC Control Register B
Setting this bit will start an ADC conversion. Bit is cleared by hardware when the conversion has
started. Writing this bit is equivalent to writing the START bits inside the ADC channel register.
• Bit 1 – FLUSH: ADC Flush:
Writing this bit to one will flush the ADC. When this is done the ADC Clock will be restarted on
the next Peripheral clock edge and any ongoing conversion in progress is aborted and lost.
After the flush and the ADC Clock restart, any new conversions pending will start.
• Bit 0 – ENABLE: ADC Enable
Setting this bit enables the ADC.
• Bits 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility reasons, always write these
bits to zero when this register is written.
• Bit 4 - CONVMODE: ADC Conversion Mode
This bit controls whether the ADC should work in signed or unsigned mode. By default this bit is
zero and the ADC is then configured for unsigned mode where single ended and internal signals
can be measured. When this bit is set to one the ADC is configured for signed mode where also
differential input can be used.
• Bit 3 - FREERUN: ADC Free Running Mode
This bit controls the free running mode for the ADC. Once a conversion is finished, the next input
will be sampled and converted.
• Bits 2:1 - RESOLUTION[1:0]: ADC Conversion Result Resolution
These bits define whether the ADC completes the conversion at 12- or 8-bit result. They also
define whether the 12-bit result is left or right oriented in the 16-bit result registers.
See
Table 20-1.
• Bit 0 - Reserved
This bit is unused and reserved for future use. For compatibility reasons, always write this bit to
zero when this register is written.
Bit
+0x01
Read/Write
Initial Value
RESOLUTION[1:0]
Table 20-1 on page 235
00
01
10
11
7
–
R
0
ADC Conversion Result resolution
R
6
–
0
Group Configuration
for possible settings.
R
5
–
0
LEFT12BIT
12BIT
8BIT
CONVMODE
R/W
4
0
FREERUN
R/W
3
0
Description
12-bit result, right adjusted
Reserved
8-bit result, right adjusted
12-bit result, left adjusted
R/W
RESOLUTION[1:0]
2
0
R/W
1
0
XMEGA D
R
0
–
0
CTRLB
235