ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 13

• Manufacturer Part Number: ATxmega32D4
• Manufacturer: Atmel Corporation

Specifications of ATxmega32D4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 4
• Twi (i2c): 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 14
• Input Capture Channels: 14
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.12.2
3.13
3.14
3.14.1
8210B–AVR–04/10
Fuse Lock
Register Description
Sequence for execution of protected SPM/LPM
CCP - Configuration Change Protection Register
Once the correct signature is written by the CPU, interrupts will be ignored for the configuration
change enable period. Any interrupt request (including Non-Maskable Interrupts) during the
CPP period will set the corresponding interrupt flag as normal and the request is kept pending.
After the CPP period any pending interrupts are executed according to their level and priority.
For some system critical features it is possible to program a fuse to disable all changes in the
associated I/O control registers. If this is done, it will not be possible to change the registers from
the user software, and the fuse can only be reprogrammed using an external programmer.
Details on this are described in the datasheet module where this feature is available.
• Bit 7:0 - CCP[7:0] - Configuration Change Protection
The CCP register must be written with the correct signature to enable change of the protected
I/O register or execution of the protected instruction for a maximum of 4 CPU instruction cycles.
All interrupts are ignored during these cycles. After these cycles interrupts automatically handled
again by the CPU, and any pending interrupts will be executed according to their level and prior-
ity. When the Protected I/O register signature is written, CCP[0] will read as one as long as the
protected feature is enabled. Similarly when the Protected SPM/LPM signature is written CCP[1]
will read as one as long as the protected feature is enabled. CCP[7:2] will always be read as
zero.
Table 3-1.
Bit
+0x04
Read/Write
Initial Value
1. The application code writes the signature for execution of protected SPM/LPM to the
2. Within 4 instruction cycles, the application code must execute the appropriate instruc-
CCP register.
tion. The protected change is immediately disabled if the CPU performs write
operations to the data memory, or if SLEEP is executed.
Table 3-1 on page 13
Signature
0x9D
0xD8
W
7
0
Modes of CPU Change Protection
W
6
0
Group Configuration
shows the signature for the various modes.
W
5
0
IOREG
SPM
W
4
0
CCP[7:0]
Description
Protected SPM/LPM
Protected IO register
W
3
0
W
2
0
W
1
0
XMEGA D
W
0
0
CCP
13