ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 53
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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5.8.3
5.8.4
8210B–AVR–04/10
STROBE – Event Strobe Register
DATA – Event Data Register
A single event lasting for one peripheral clock cycle will be generated.
• Bit 7:4 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bit to zero when this register is written.
• Bit 3:0 - STROBE[3:0] - Event Strobe bit Register
If any of the STROBE bit is unequal to zero or simply written, each event channel will be set
according to the STROBE[n] and corresponding DATA[n] bit setting.
This register must be written before the STROBE register, for details
Strobe Register” on page 53.
• Bit 7:4 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 3:0 - DATA[3:0] - Event Data bit Register
Any of the DATA bits contains the data value when manually generating a data event.
Bit
+0x11
Read/Write
Initial Value
Bit
+0x10
Read/Write
Initial Value
R
R
7
–
0
7
–
0
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
R
4
–
R
0
4
–
0
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
STROBE[3:0]
DATA[3:0]
R/W
R/W
1
0
1
0
See ”STROBE – Event
XMEGA D
R/W
R/W
0
0
0
0
STROBE
DATA
53