ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 264

• Manufacturer Part Number: ATxmega32D4
• Manufacturer: Atmel Corporation

Specifications of ATxmega32D4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 4
• Twi (i2c): 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 14
• Input Capture Channels: 14
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.4.1
22.4.2
22.4.3
22.4.4
22.4.5
22.4.5.1
8210B–AVR–04/10
Accessing Internal Interfaces
NVM Programming Key
Exception handling
Reset signalling
Instruction Set
LDS - Load data from PDIBUS Data Space using direct addressing
After an external programmer has established communication with the PDI, the internal inter-
faces are not accessible by default. To get access to the NVM Controller and the NVM
memories for programming, a unique key must be signalized by using the KEY instruction. The
internal interfaces is accessed as one linear address space using a dedicated bus (PDIBUS)
between the PDI and the internal interfaces.
The key that must be sent using the KEY instruction is 64 bits long. The key that will enable
NVM Programming is:
0x1289AB45CDD888FF
There are several situations that are considered exceptions from normal operation. The excep-
tions depends on whether the PDI is in RX - or TX mode.
While the PDI is in RX mode, these exceptions are defined as:
While the PDI is in TX mode, these exceptions are defined:
All exceptions are signalized to the PDI Controller. All on-going operations are then aborted and
the PDI is put in the ERROR state. The PDI will remain in this state until a BREAK is sent from
the External Programmer, and this will bring the PDI back to its default RX state.
Due to this mechanism the programmer can always synchronize the protocol by transmitting two
successive BREAK characters.
Through the Reset Register, the programmer can issue a reset and force the device into reset.
After clearing the Reset Register, reset is released unless some other reset source is active.
The PDI has a small instructions set that is used for all access to the PDI itself and to the internal
interfaces.All instructions are byte instructions. Most of the instructions require a number of byte
operands following the instruction. The instructions allow to external programmer to access the
PDI Controller, the NVM Controller and the NVM memories.
The LDS instruction is used to load data from the PDIBUS Data Space for serial read-out. The
LDS instruction is based on direct addressing, which means that the address must be given as
an argument to the instruction. Even though the protocol is based on byte-wise communication,
the LDS instruction supports multiple-bytes address - and data access. Four different
address/data sizes are supported; byte, word, 3 bytes, and long (4 bytes). It should be noted that
multiple-bytes access is internally broken down to repeated single-byte accesses. The main
• PDI:
• PDI:
– The physical layer detects a parity error.
– The physical layer detects a frame error.
– The physical layer recognizes a BREAK character (also detected as a frame error).
– The physical layer detects a data collision.
XMEGA D
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