ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 90
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
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9.4
9.5
9.6
8210B–AVR–04/10
Window Mode Operation
Watchdog Timer clock
Configuration Protection and Lock
In window mode operation the WDT uses two different timeout periods, a "closed" window time-
out period (TO
defines a duration from 8 ms to 8s where the WDT cannot be reset: if the WDT is reset in this
period the WDT will issue a system reset. The normal WDT timeout period, which is also 8 ms to
8s, defines the duration of the "open" period, in which the WDT can (and should) be reset. The
open period will always follow the closed period, so the total duration of the timeout period is the
sum of the closed window and the open window timeout periods. The default closed window tim-
eout period is controlled by fuses. The window mode operation is illustrated in
Figure 9-2.
The WDT is clocked from the 1 kHz output from the internal 32 kHz Ultra Low Power (ULP) oscil-
lator. Due to the ultra low power design, the oscillator is not very accurate so the exact timeout
period may vary from device to device. When designing software which uses the WDT, this
device-to-device variation must be kept in mind to ensure that the timeout periods used are valid
for all devices. For more information on the ULP oscillator accuracy, consult the device
datasheet.
The WDT is designed with two security mechanisms to avoid unintentional changes of the WDT
settings.
The first mechanism is the Configuration Change Protection mechanism, employing a timed
write procedure for changing the WDT control registers. In addition, for the new configuration to
be written to the control registers, the register’s Change Enable bit must be written at the same
time.
The second mechanism is to lock the configuration by setting the WDT lock fuse. When this fuse
is set, the Watchdog Time Control Register can not be changed, hence the WDT can not be dis-
abled from software. After system reset the WDT will resume at configured operation. When the
WDT lock fuse is programmed the window mode timeout period cannot be changed, but the win-
dow mode itself can still be enabled or disabled.
TO
TO
WDTW
WDT
WDTW
Window mode operation.
= 8
= 8
WDT Count
) and the normal timeout period (TO
5
10
15
TO
WDTW
20
TO
25
WDT
WDT
). The closed window timeout period
30
Timely WDT
Reset
35
Early WDT Reset
t [ms]
System Reset
XMEGA D
Figure
9-2.
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