ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 25
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
4.12.9
4.12.10
8210B–AVR–04/10
CTRLB - Non-Volatile Memory Control Register B
INTCTRL - Non-Volatile Memory Interrupt Control Register
• Bit 7:4 - Reserveds
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3 - EEMAPEN: EEPROM Data Memory Mapping Enable
Writing this bit to one will enable Data Memory Mapping of the EEPROM section. The EEPROM
can then be accessed using Load and Store instructions.
• Bit 2 - FPRM: Flash Power Reduction Mode
Writing this bit to one will enable power saving for the flash memory. The section not being
accessed will be turned off like in sleep mode. If code is running from Application Section, the
Boot Loader Section will be turned off and vice versa. If access to the section that is turned off is
required, the CPU will be halted equally long to the start-up time from the Idle sleep mode. This
bit is protected by the Configuration Change Protection (CCP) mechanism, refer to
tion Change Protection” on page 12
• Bit 1 - EPRM: EEPROM Power Reduction Mode
Writing this bit to one will enable power saving for the EEPROM memory. The EEPROM will
then be powered down equal to entering sleep mode. If access is required, the bus master will
be halted equally long as the start-up time from Idle sleep mode. This bit is protected by the
Configuration Change Protection (CCP) mechanism, refer to
on page 12
• Bit 0 - SPMLOCK: SPM Locked
The SPM Locked bit can be written to prevent all further self-programming. The bit is cleared at
reset and cannot be cleared from software. This bit is protected by the Configuration Change
Protection (CCP) mechanism, refer to
on the CCP.
• Bit 7:4 - Reserved Bits
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x0D
Read/Write
Initial Value
Bit
+0x0C
Read/Write
Initial Value
for details on the CCP.
R
7
–
0
R
7
–
0
R
6
–
0
R
6
–
0
R
5
–
0
R
5
–
0
for details on the CCP.
R
4
–
0
”Configuration Change Protection” on page 12
EEMAPEN
R
4
–
0
R/W
3
0
R/W
3
0
SPMLVL[1:0]
FPRM
R/W
2
0
”Configuration Change Protection”
R/W
2
0
EPRM
R/W
1
0
R/W
1
0
EELVL[1:0]
SPMLOCK
XMEGA D
R/W
0
0
R/W
0
0
”Configura-
for details
INTCTRL
CTRLB
25