ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 174
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
16.3.7
16.3.8
8210B–AVR–04/10
Clock and Clock Stretching
Arbitration
All devices connected to the bus are allowed to stretch the low period of the clock to slow down
the overall clock frequency or to insert wait states while processing data. A device that needs to
stretch the clock can do this by holding/forcing the SCL line low after it detects a low level on the
line.
Three types of clock stretching can be defined as shown in
Figure 16-8. Clock Stretching
If the device is in a sleep mode and a START condition is detected the clock is stretched during
the wake-up period for the device.
A slave device can slow down the bus frequency by stretching the clock periodically on a bit
level. This allows the slave to run at a lower system clock frequency. However, the overall per-
formance of the bus will be reduced accordingly. Both the master and slave device can
randomly stretch the clock on a byte level basis before and after the ACK/NACK bit. This pro-
vides time to process incoming or prepare outgoing data, or performing other time critical tasks.
In the case where the slave is stretching the clock the master will be forced into a wait-state until
the slave is ready and vice versa.
A master can only start a bus transaction if it has detected that the bus is idle. As the TWI bus is
a multi master bus, it is possible that two devices initiate a transaction at the same time. This
results in multiple masters owning the bus simultaneously. This is solved using an arbitration
scheme where the master loses control of the bus if it is not able to transmit a high level on the
SDA line. The masters who lose arbitration must then wait until the bus becomes idle (i.e. wait
for a STOP condition) before attempting to reacquire bus ownership. Slave devices are not
involved in the arbitration procedure.
SDA
SCL
S
Wakeup clock
stretching
bit 7
bit 6
Periodic clock
stretching
Figure
bit 0
16-8.
ACK/NACK
Random clock
XMEGA D
stretching
174