AD9125 Analog Devices, AD9125 Datasheet - Page 21

• Manufacturer Part Number: AD9125
• Manufacturer: Analog Devices

Specifications of AD9125

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

Register Name
Compare
SED I LSBs
SED I MSBs
SED Q LSBs
SED Q MSBs
Die Revsion
DEVICE CONFIGURATION REGISTER DESCRIPTIONS
Table 11. Device Configuration Register Descriptions
Register
Name
Comm
Power Control
Data Format
Interrupt Enable 1
Q1 MSBs
Addr
(Hex)
0x6F
0x70
0x71
0x72
0x73
0x7F
Address
(Hex)
0x00
0x01
0x03
0x04
Bit 7
Bits
7
6
5
7
6
5
4
0
7
6
5
[1:0]
7
6
5
4
3
2
Bit 6
Name
SDIO
LSB_FIRST
Reset
Power-down DAC I
Power-down DAC Q
Power-down data
receiver
Power-down auxiliary
ADC
PLL lock status
Binary data format
Q data first
MSB swap
Data bus width
Enable PLL lock lost
Enable PLL lock
Enable sync signal lost
Enable sync signal lock
Enable sync phase
locked
Enable soft FIFO sync
Bit 5
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Errors detected Q_BITS[15:8]
Errors detected I_BITS[15:8]
Errors detected Q_BITS[7:0]
Errors detected I_BITS[7:0]
Compare Value Q1[15:8]
Bit 4
Description
SDIO operation.
0 = SDIO operates as an input only.
1 = SDIO operates as a bidirectional input/output.
Serial port communication LSB or MSB first.
0 = MSB first.
1 = LSB first.
1 = device is held in reset when this bit is written high
and is held there until the bit is written low.
1 = powers down DAC I.
1 = powers down DAC Q.
1 = powers down the input data receiver.
1 = powers down the auxiliary ADC for temperature
sensor.
1 = PLL is locked.
0 = input data is in twos complement format.
1 = input data is in binary format.
Indicates I/Q data pairing on data input.
0 = I data sent to data receiver first.
1 = Q data sent to data receiver first.
Swaps the bit order of the data input port.
0 = order of the data bits corresponds to the pin
descriptions.
1 = bit designations are swapped; most significant bits
become the least significant bits.
Data receiver interface mode.
00 = dual-word mode; 32-bit interface bus width.
01 = word mode; 16-bit interleaved interface bus width.
10 = byte mode; 8-bit interleaved interface bus width.
11 = invalid.
See the CMOS Input Data Ports section for details on
the operation of the different interface modes.
1 = enables interrupt for PLL lock lost.
1 = enables interrupt for PLL lock.
1 = enables interrupt for sync signal lock lost.
1 = enables interrupt for sync signal lock.
1 = enables interrupt for clock generation ready.
1 = enables interrupt for soft FIFO reset.
Revision[3:0]
Bit 3
Bit 2
Bit 1
Bit 0
AD9125
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default
0xAA
0x00
0x00
0x00
0x00
0x0C