AD9125 Analog Devices, AD9125 Datasheet - Page 29

• Manufacturer Part Number: AD9125
• Manufacturer: Analog Devices

Specifications of AD9125

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

CMOS INPUT DATA PORTS
The AD9125 input data port consists of a data clock (DCI),
data bus, and FRAME signal. The data port can be configured
to operate in three modes: dual-word mode, word mode, and
byte mode.
In dual-word mode, I and Q data is received simultaneously on
two 16-pin buses. One bus receives I datapath input words, and
the other bus receives Q datapath input words. In word mode,
one 16-pin bus is used to receive interleaved I and Q input
words. In byte mode, an 8-pin bus is used to receive interleaved
I and Q input bytes. The pin assignments of the bus in each
mode is described in Table 12.
Table 12. Data Bit Pin Assignments for Data Input Modes
Mode
Dual Word
Word
Byte
In byte and word modes, a FRAME signal is required for
controlling which DAC receives the data. In dual-word mode,
the FRAME signal is not required because each DAC has a
dedicated bus.
DUAL-WORD MODE
In dual-word mode, the DCI signal is supplied as a qualifying
clock that is time aligned with the input data. The rising edge of
the DCI signal should be aligned with the changing data of each
of the I and Q input data streams.
Q DATA
I DATA
DCI
Figure 42. Timing Diagram for Dual-Word Mode
Data Bus Pin Assignments
I data: D[31:16]
Q data: D[15:0]
I and Q data: D[29:28], D[25:24], D[21:20], D[17:16],
D[15:14], D[11:10], D[7:6], D[3:2]
I and Q data: D[21:20], D[17:16], D[15:14], D[11:10]
Q
I
1
1
Q
I
2
2
Q
I
3
3
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WORD MODE
In word mode, the DCI signal is supplied as a qualifying clock
that is time aligned with the input data. The rising edge of the
DCI signal should be aligned with the changing data of the
interleaved I and Q input data stream. The FRAME signal
indicates to which DAC the data is sent. When FRAME is high,
data is sent to the I DAC. When FRAME is low, data is sent to
the Q DAC. For 14- and 12-bit resolution devices, the two and
four LSBs are not significant, respectively. The complete timing
diagram is shown in Figure 43.
BYTE MODE
In byte mode, the DCI signal is supplied as a qualifying clock
that is time aligned with the input data. The rising edge of the
DCI signal should be aligned with the changing data of the
interleaved I and Q input data stream. The FRAME signal
indicates to which DAC the data is sent. When FRAME is high,
data is sent to the I DAC. When FRAME is low, data is sent to
the Q DAC. Both bytes must be written to each datapath for
proper operation. For 14- and 12-bit resolution devices, the
LSBs in the second byte are not significant. The complete
timing diagram is shown in Figure 44.
Q DATA
FRAME
I AND
DCI
Q
Q DATA
FRAME
LSB
I AND
DCI
I
1MSB
Figure 43. Timing Diagram for Word Mode
Figure 44. Timing Diagram for Byte Mode
I
1LSB
I
1
Q
1MSB
Q
1LSB
Q
1
I
2MSB
I
2LSB
I
2
Q
2MSB
AD9125
Q
2LSB