AD9125 Analog Devices, AD9125 Datasheet - Page 22

• Manufacturer Part Number: AD9125
• Manufacturer: Analog Devices

Specifications of AD9125

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

AD9125
Register
Name
Interrupt Enable 2
Event Flag 1
Event Flag 2
Clock Receiver
Control
1
1
Address
(Hex)
0x05
0x06
0x07
0x08
Bits
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
4
3
2
7
6
5
4
Name
Enable FIFO Warning 1
Enable FIFO Warning 2
Set to 0
Set to 0
Set to 0
Enable AED comparison
pass
Enable AED comparison
fail
Enable SED comparison
fail
Set to 0
Set to 0
PLL lock lost
PLL locked
Sync signal lost
Sync signal locked
Sync phase locked
Soft FIFO sync
FIFO Warning 1
FIFO Warning 2
AED comparison pass
AED comparison fail
SED comparison fail
DACCLK duty correction
REFCLK duty correction
DACCLK cross-correction
REFCLK cross-correction
Rev. 0 | Page 22 of 56
Description
1 = enables interrupt for FIFO Warning 1.
1 = enables interrupt for FIFO Warning 2.
Set this bit to 0.
Set this bit to 0.
Set this bit to 0.
1 = enables interrupt for AED comparison pass.
1 = enables interrupt for AED comparison fail.
1 = enables interrupt for SED comparison fail.
Set this bit to 0.
Set this bit to 0.
1 = indicates that the PLL, which had been previously
locked, has unlocked from the reference signal. This is a
latched signal.
1 = indicates that the PLL has locked to the reference
clock input.
1 = indicates that the sync logic, which had been
previously locked, has lost alignment. This is a latched
signal.
1 = indicates that the sync logic did achieve sync
alignment. This is indicated when no phase changes
were requested for at least a few full averaging cycles.
1 = indicates that the internal digital clock generation logic
is ready. This occurs when internal clocks are present and
stable.
1 = indicates that a FIFO reset originating from a serial
port-based request has successfully completed. This is a
latched signal.
1 = indicates that the difference between the FIFO read
and write pointers is 1.
1 = indicates that the difference between the FIFO read
and write pointers is 2.
1 = indicates that the SED logic detected a valid input
data pattern compared with the preprogrammed
expected values. This is a latched signal.
1 = indicates that the SED logic detected an invalid
input data pattern compared with the preprogrammed
expected values. This is a latched signal that auto-
matically clears when eight valid I/Q data pairs are
received.
1 = indicates that the SED logic detected an invalid
input data pattern compared with the preprogrammed
expected values. This is a latched signal.
1 = enables duty-cycle correction on the DACCLK input.
1 = enables duty-cycle correction on the REFCLK input.
1 = enables differential crossing correction on the DACCLK
input.
1 = enables differential crossing correction on the
REFCLK input.
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1