AD9125 Analog Devices, AD9125 Datasheet - Page 53

• Manufacturer Part Number: AD9125
• Manufacturer: Analog Devices

Specifications of AD9125

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

INTERFACE TIMING VALIDATION
The AD9125 provides on-chip sample error detection (SED)
circuitry that simplifies verification of the input data interface.
The SED compares the input data samples captured at the digital
input pins with a set of comparison values, which are loaded into
registers through the SPI port. Differences between these values
are detected and stored. Options are available for customizing SED
test sequencing and error handling.
SED OPERATION
The SED circuitry operates on a data set made up of four 16-bit
input words, denoted as I0, Q0, I1, and Q1. To properly align the
input samples, the first I and Q data-words (that is, I0 and Q0)
are indicated by asserting the FRAME signal for a minimum of
two complete input samples.
Figure 87 shows the input timing of the interface in dual-word
mode. The FRAME signal can be issued once at the start of the
data transmission, or it can be asserted repeatedly at intervals
coinciding with the I0 and Q0 data-words.
In word mode, the FRAME signal required to align the data
samples needs to be extended. The FRAME signal can be issued
once at the start of the data transmission, or it can be asserted
repeatedly at intervals coinciding with the I0 and Q0 data-words.
The SED has three flag bits (Register 0x67, Bit 0, Bit 1, and
Bit 5) that indicate the results of the input sample comparisons.
The sample error detected bit (Register 0x67, Bit 5) is set when
an error is detected and remains set until the bit is cleared. The
SED also provides registers that indicate which input data bits
experienced errors (Register 0x70 through Register 0x73).
These bits are latched and indicate the accumulated errors
detected until cleared.
The autoclear mode has two effects: it activates the compare fail
bit and the compare pass bit (Register 0x67, Bit 1 and Bit 0) and
Table 28. Progression of Comparison Outcomes and the Resulting SED Register Values
Compare Results (Pass/Fail)
Register 0x67, Bit 5 (Sample Error Detected)
Register 0x67, Bit 1 (Compare Fail)
Register 0x67, Bit 0 (Compare Pass)
Register 0x70 to Register 0x73 (Errors Detected x_BITS[15:0])
1
2
N = nonzero.
Z = all 0s.
D[31:16]
FRAME
FRAME
D[15:0]
D[15:0]
Figure 87. Timing Diagram for Dual-Word Mode SED Operation
Figure 88. Timing Diagram for Two-Port Mode SED Operation
Q0
I0
I0
Q0
Q1
I1
Q0
I1
I0
Q1
Q1
I1
Q0
I0
I0
P
0
0
1
Z
Q0
1
Rev. 0 | Page 53 of 56
F
1
1
0
N
2
F
1
1
0
N
2
F
1
1
0
N
2
changes the behavior of Register 0x70 through Register 0x73. The
compare pass bit is set if the last comparison indicated that the
sample was error free. The compare fail bit is set if an error is
detected. The compare fail bit is automatically cleared by the
reception of eight consecutive error-free comparisons. When
autoclear mode is enabled, Register 0x70 through Register 0x73
accumulate errors as previously described but reset to all 0s after
eight consecutive error-free sample comparisons are made.
The sample error, compare pass, and compare fail flags can be
configured to trigger an IRQ when active, if desired. This is
done by enabling the appropriate bits in the Event Flag 2 register
(Register 0x07).
comparison results and the corresponding states of the error flags.
SED EXAMPLE
Normal Operation
The following example illustrates the SED configuration for
continuously monitoring the input data and assertion of an IRQ
when a single error is detected.
1.
2.
3.
If IRQ is asserted, read Register 0x67 and Register 0x70 through
Register 0x73 to verify that a SED error was detected and to deter-
mine which input bits were in error. The bits in Register 0x70
through Register 0x73 are latched; therefore, the bits indicate
any errors that occurred on those bits throughout the test, not
just the errors that caused the error detected flag to be set.
P
1
1
1
N
Write to the following registers to enable the SED and load
the comparison values.
Register 0x67: 0x80
Register 0x68: I0[7:0]
Register 0x69: I0[15:8]
Register 0x6A: Q0[7:0]
Register 0x6B: Q0[15:8]
Register 0x6C: I1[7:0]
Register 0x6D: I1[15:8]
Register 0x6E: Q1[7:0]
Register 0x6F: Q1[15:8]
Comparison values can be chosen arbitrarily; however,
choosing values that require frequent bit toggling provides
the most robust test.
Enable the SED error detect flag to assert the IRQ pin by
writing 0x04 to Register 0x05.
Begin transmitting the input data pattern.
2
P
1
1
1
N
2
1
1
1
P
N
Table 28
2
P
1
1
1
N
2
shows a progression of the input sample
P
1
1
1
N
2
P
1
1
1
N
2
P
1
1
1
N
2
P
1
1
1
N
2
1
0
P
1
Z
1
F
1
1
0
N
AD9125
2
P
1
1
1
N
2
F
1
1
0
N
2