AD9125 Analog Devices, AD9125 Datasheet - Page 45

• Manufacturer Part Number: AD9125
• Manufacturer: Analog Devices

Specifications of AD9125

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

DEVICE POWER DISSIPATION
The AD9125 has four supply rails: AVDD33, IOVDD, DVDD18,
and CVDD18.
The AVDD33 supply powers the DAC core circuitry. The power
dissipation of the AVDD33 supply rail is independent of the digital
operating mode and sample rate. The current drawn from the
AVDD33 supply rail is typically 57 mA (188 mW) when the
full-scale current of the I and Q DACs is set to the nominal value
of 20 mA. Changing the full-scale current directly impacts the
supply current drawn from the AVDD33 rail. For example, if
the full-scale current of the I DAC and the Q DAC is changed to
10 mA, the AVDD33 supply current drops by 20 mA to 37 mA.
The IOVDD voltage supplies the serial port I/O pins, the RESET
pin, and the IRQ pin. The voltage applied to the IOVDD pin can
range from 1.8 V to 3.3 V. The current drawn by the IOVDD
supply pin is typically 3 mA.
The DVDD18 supply powers all of the digital signal processing
blocks of the device. The power consumption from this supply
is a function of which digital blocks are enabled and the frequency
at which the device is operating.
The CVDD18 supply powers the clock receiver and clock
distribution circuitry. The power consumption from this
supply varies directly with the operating frequency of the
device. CVDD18 also powers the PLL. The power dissipation
of the PLL is typically 80 mA when enabled.
Figure 76 through Figure 80 detail the power dissipation of the
AD9125 under a variety of operating conditions. All of the graphs
are taken with data being supplied to both the I and Q channels.
The power consumption of the device does not vary significantly
with changes in the coarse modulation mode selected or analog
output frequency. Graphs of the total power dissipation are shown
along with the power dissipation of the DVDD18 and CVDD18
supplies.
Maximum power dissipation can be estimated to be 20% higher
than the typical power dissipation.
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Figure 76. Total Power Dissipation vs. f
Figure 77. DVDD18 Power Dissipation vs. f
1800
1600
1400
1200
1000
1400
1200
1000
Figure 78. CVDD18 Power Dissipation vs. f
800
600
400
200
800
600
400
200
250
200
150
100
50
0
0
0
0
0
0
50
50
50
100
100
100
Inverse Sinc
Inverse Sinc
8×
8×
f
f
f
DATA
DATA
DATA
8×
150
150
150
(MHz)
(MHz)
(MHz)
DATA
4×
Without PLL, Fine NCO, and
DATA
200
200
200
DATA
Without Fine NCO and
with PLL Disabled
2×
4×
1×
4×
2×
1×
250
250
250
2×
1×
AD9125
300
300
300