ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 70

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

ADuC7124/ADuC7126
I
The ADuC7124/ADuC7126 incorporate two I
that can be configured as a fully I
device or as a fully I
channels are identical. Therefore, the following descriptions
apply to both channels.
The two pins used for data transfer, SDA and SCL, are configured
in a wire-AND’ e d format that allows arbitration in a multimaster
system. These pins require external pull-up resistors. Typical
pull-up values are between 4.7 kΩ and 10 kΩ.
The I
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer (read or/write) during the
initial address transfer. If the master does not lose arbitration
and the slave acknowledges, the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I
any given time. The same I
support master and slave modes.
The I
following features:
•
•
•
•
•
•
•
•
2
C
Support for repeated start conditions. In master mode, the
ADuC7124/ADuC7126 can be programmed to generate a
repeated start. In slave mode, the ADuC7124/ADuC7126
recognizes repeated start conditions.
In master and slave mode, the part recognizes both 7-bit
and 10-bit bus addresses.
In I
continuous reads from a single slave up to 512 bytes in a
single transfer sequence.
Clock stretching is supported in both master and slave modes.
In slave mode, the ADuC7124/ADuC7126 can be pro-
grammed to return a NACK. This allows the validiation of
checksum bytes at the end of I
Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for
I
The transmit and receive circuits in both master and slave
mode contain 2-byte FIFOs. Status bits are available to the
user to control these FIFOs.
2
2
2
2
C peripheral can only be configured as a master or slave at
C bus peripheral address in the I
C interface on the ADuC7124/ADuC7126 includes the
C hardware testing in loopback mode.
2
C master mode, the ADuC7124/ADuC7126 supports
2
C bus compatible slave device. Both I
2
C channel cannot simultaneously
2
C system consists of a master
2
C-compatible I
2
C transfers.
2
C bus system is
2
C peripherals
2
C bus master
2
C
Rev. B | Page 70 of 104
Configuring External Pins for I
The I
P1.1 for I2C0 and P1.2 and P1.3 for I2C1.
P1.0 and P1.2 are the I
the I
SDA0), Bit 0 and Bit 4 of the GP1CON register must be set to 1
to enable I
(SCL1, SDA1), Bit 8 and Bit 12 of the GP1CON register must
be set to 1 to enable I
Input/Output section.
Serial Clock Generation
The I
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2CxDIV MMR as follows:
where:
f
DIVH is the high period of the clock.
DIVL is the low period of the clock.
Therefore, for 100 kHz operation,
and for 400 kHz
The I2CxDIV register corresponds to DIVH:DIVL.
I
Slave Mode
In slave mode, the I2CxID0, I2CxID1, I2CxID2, and I2CxID3
registers contain the device IDs. The device compares the four
I2CxIDx registers to the address byte received from the bus
master. To be correctly addressed, the seven MSBs of either ID
register must be identical to the seven MSBs of the first received
address byte. The LSB of the ID registers (the transfer direction
bit) is ignored in the process of address recognition.
The ADuC7124/ADuC7126 also support 10-bit addressing
mode. When Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, one
10-bit address is supported in slave mode and is stored in the
I2CxID0 and I2CxID1 registers. The 10-bit address is derived as
follows:
I2CxID0[0] is the read/write bit and is not part of the I
address.
I2CxID0[7:1] = Address Bits[6:0].
I2CxID1[2:0] = Address Bits[9:7].
I2CxID1[7:3] must be set to 11110b.
UCLK
2
C Bus Addresses
2
DIVH = DIVL = 0xCF
DIVH = 0x28, DIVL = 0x3C
is the clock before the clock divider.
2
C data signals. For instance, to configure I2C0 pins (SCL0,
2
f
C pins of the ADuC7124/ADuC7126 device are P1.0 and
C master in the system generates the serial clock for a
SERIAL
2
C mode. On the other hand, to configure I2C1 pins
CLOCK
=
2 (
2
C mode, as shown in the General-Purpose
+
2
C clock signals, and P1.1 and P1.3 are
DIVH
f
UCLK
)
+
(2
2
C Functionality
+
DIVL
)
2
C