ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 8

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ADUC7126

Manufacturer Part Number
ADUC7126
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7126

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Gpio Pins
40
Adc # Channels
16
Other
PWM

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ADuC7124/ADuC7126
Parameter
ESD TESTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TIMING SPECIFICATIONS
I
Table 2. I
Parameter
t
t
t
t
t
t
t
t
t
t
Table 3. I
Parameter
t
t
t
t
t
t
t
t
t
t
2
L
H
SHD
DSU
DHD
RSU
PSU
BUF
R
F
L
H
SHD
DSU
DHD
RSU
PSU
BUF
R
F
All ADC channel specifications are guaranteed during normal core operation.
Apply to all ADC input channels.
Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
Not production tested but supported by design and/or characterization data on production release.
Measured using the factory-set default values in ADCOF and ADCGN with an external
system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
The input signal can be centered on any dc common-mode voltage (V
DAC linearity is calculated using a reduced code range of 100 to 3995.
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V
Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
3.6 V supply, and sleep mode with 3.6 V supply.
C Timing
Retention lifetime equivalent at junction temperature (T
Test carried out with a maximum of eight I/Os set to a low output level.
Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
IOV
This current must be added to the AV
HBM Passed Up To
FICDM Passed Up To
DD
power supply current increases typically by 2 mA during a Flash/EE erase cycle.
2
2
C Timing in Fast Mode (400 kHz)
C Timing in Standard Mode (100 kHz)
Description
SCLK low pulse width
SCLK high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCLK and SDATA
Fall time for both SCLK and SDATA
Description
SCLK low pulse width
SCLK high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCLK and SDATA
Fall time for both SCLK and SDATA
DD
current.
Min
J
) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
Typ
CM
) as long as this value is within the ADC voltage input range specified.
Rev. B | Page 8 of 104
Max
3
1.5
REF
AD845
.
op amp as an input buffer stage as shown in Figure 37. Based on external ADC
Unit
kV
kV
Test Conditions/Comments
2.5 V reference, T
Min
4.7
4.0
4.0
250
0
4.7
4.0
4.7
Min
200
100
300
100
0
100
100
1.3
Slave
A
Max
300
300
= 25°C
Slave
Typ
1360
1140
740
400
800
200
Max
3.45
1
300
Master
Unit
µs
ns
µs
ns
µs
µs
µs
µs
µs
ns
Unit
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns

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