ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 79
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ADUC7126
Manufacturer Part Number
ADUC7126
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet
1.ADUC7126.pdf
(104 pages)
Specifications of ADUC7126
Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Gpio Pins
40
Adc # Channels
16
Other
PWM
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Table 113. PWMCON0 MMR Bit Descriptions
Bit
14
13
12
11
10
9
[8:6]
5
4
3
2
1
0
1
In H-bridge mode, HMODE = 1. See Table 114 to determine the PWM outputs.
Name
SYNC
PWM5INV
PWM3INV
PWM1INV
PWMTRIP
ENA
PWMCP[2:0]
POINV
HOFF
LCOMP
DIR
HMODE
PWMEN
Description
Enables PWM synchronization.
Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on the P3.7/PWM
Cleared by the user to ignore transitions on the P3.7/PWM
Set to 1 by the user to invert PWM5.
Cleared by the user to use PWM5 in normal mode.
Set to 1 by the user to invert PWM3.
Cleared by the user to use PWM3 in normal mode.
Set to 1 by the user to invert PWM1.
Cleared by the user to use PWM1 in normal mode.
Set to 1 by the user to enable PWM trip interrupt. When the PWM trip input (Pin P3.6/PWM
is low, the PWMEN bit is cleared and an interrupt is generated.
Cleared by the user to disable the PWMTRIP interrupt.
If HOFF = 0 and HMODE = 1; note that, if not in H-bridge mode, this bit has no effect.
Set to 1 by the user to enable PWM outputs.
Cleared by the user to disable PWM outputs.
If HOFF = 1 and HMODE = 1, see Table 114.
PWM clock prescaler bits. Sets the UCLK divider.
[000] = UCLK/2.
[001] = UCLK/4.
[010] = UCLK/8.
[011] = UCLK/16.
[100] = UCLK/32.
[101] = UCLK/64.
[110] = UCLK/128.
[111] = UCLK/256.
Set to 1 by the user to invert all PWM outputs.
Cleared by the user to use PWM outputs as normal.
High side off.
Set to 1 by the user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low.
Cleared by the user to use the PWM outputs as normal.
Load compare registers.
Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of
the PWM timer from 0x00 to 0x01.
Cleared by the user to use the values previously stored in the internal compare registers.
Direction control.
Set to 1 by the user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low.
Cleared by the user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low.
Enables H-bridge mode.
Set to 1 by the user to enable H-bridge mode and Bit 1 to Bit 5 of PWMCON.
Cleared by the user to operate the PWMs in standard mode.
Set to 1 by the user to enable all PWM outputs.
Cleared by the user to disable all PWM outputs.
1
SYNC
pin.
Rev. B | Page 79 of 104
SYNC
pin.
ADuC7124/ADuC7126
TRIP
or Pin P0.4/PWM
TRIP
)