ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet

Page 1

... Development tools – Full HW/SW development package – DM (Debug Module) Doc ID 13562 Rev 3 ST7LITE49M SDIP32 ST7LITE49M 4 Kbytes 384 (128) 128 2 MHz -40 to +125 °C LQFP32, SDIP32 1/188 www.st.com ...

Page 2

... Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4.1 5.4.2 5.4.3 5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.6 Data EEPROM read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.7 EEPROM control/status register (EECSR 2/188 In-circuit programming (ICP In-application programming (IAP Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read operation (E2LAT= Write operation (E2LAT= Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 13562 Rev 3 ST7LITE49M ...

Page 3

... ST7LITE49M 6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 7 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1.1 7.1.2 7.2 Multi-oscillator (MO 7.2.1 7.2.2 7.2.3 7.3 Reset sequence manager (RSM 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 System integrity management (SI 7.4.1 7.4.2 7.4.3 7.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Accumulator ( Index registers (X and Program counter (PC Condition code register (CC) ...

Page 4

... CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Interrupt software priority registers (ISPRx External interrupt control register (EICR Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 AWUFH control/status register (AWUCSR AWUFH prescaler register (AWUPR Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Doc ID 13562 Rev 3 ST7LITE49M ...

Page 5

... ST7LITE49M 10.7.1 10.7.2 11 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.1 Watchdog timer (WDG 11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 11.1.6 11.2 Dual 12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.3 Lite timer 2 (LT2 102 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3 bus interface (I 11.4.1 11.4.2 11.4.3 11.4.4 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.4.5 11.4.6 11.4.7 11.5 10-bit A/D converter (ADC 125 11.5.1 Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Introduction ...

Page 6

... General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Operating conditions with low voltage detector (LVD 142 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 143 Voltage drop between AVD flag setting and LVD reset generation . . . 143 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Doc ID 13562 Rev 3 ST7LITE49M ...

Page 7

... ST7LITE49M 13.5.1 13.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.6.1 13.6.2 13.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 13.8 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 156 13.8.1 13.8.2 13.8.3 13.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 13.9.1 13.9.2 13.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 13.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 13.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 173 14.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 14.1.1 14.1.2 14.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14 ...

Page 8

... Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 15. Setting the interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 16. Interrupt vector vs. ISPRx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 17. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 18. ST7LITE49M interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 19. Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 20. Enabling/disabling Active-halt and Halt modes Table 21. Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 22. ...

Page 9

... LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 92. Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 93. Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Table 94. Development tool order codes for the ST7LITE49M family . . . . . . . . . . . . . . . . . . . . . . . 177 Table 95. ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 96. 32-pin plastic dual in-line package, shrink 400-mil width, (mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 97 ...

Page 10

... Figure 40. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 41. PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 42. Dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 43. ST7LITE49M block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 44. Block diagram of output compare mode (single timer Figure 45. Block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 46. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 47. ...

Page 11

... ST7LITE49M Figure 49. Block diagram of One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 50. One-pulse mode and PWM timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 51. Dynamic DCR2/3 update in One-pulse mode Figure 52. Force overflow timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 53. Lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 54. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 2 Figure 55 bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 2 Figure 56 ...

Page 12

... List of figures Figure 100. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 101. 32-pin plastic dual in-line package, shrink 400-mil width, package outline 182 Figure 102. 32-pin low profile quad flat package (7x7), package outline . . . . . . . . . . . . . . . . . . . . . . . 183 12/188 Doc ID 13562 Rev 3 ST7LITE49M ...

Page 13

... The ST7LITE49M features Flash memory with byte-by-byte in-circuit programming (ICP) and in-application programming (IAP) capability. Under software control, the ST7LITE49M device can be placed in Wait, Slow, or Halt mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code ...

Page 14

... OSC1/CLKIN 14 OSC2 SSA ei2 ei0 ei1 RESET Doc ID 13562 Rev 3 ST7LITE49M PC6 32 PC5 31 PC4/LTIC 30 PC3/ICCCLK 29 PC2/ICCDATA 28 PC1/AIN9 27 PC0/AIN8 26 PB7/AIN7 25 PB6/AIN6 24 PB5/AIN5 23 PB4/AIN4 22 PB3/AIN3 21 PB2/AIN2 20 PB1/AIN1/CLKIN 19 ...

Page 15

... ST7LITE49M Legend / Abbreviations for Type input output supply In/Output level: C Output level high sink (on N-buffer only) Port and control configuration: ● Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ● Output open-drain push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state ...

Page 16

... ei0 I and V pins to the supply voltage and all V DD DDA Doc ID 13562 Rev 3 ST7LITE49M Main function Alternate Output (after function reset Port Port B1 External clock source Port Port B3 ...

Page 17

... The size of Flash Sector 0 and other device options are configurable by option bytes (refer to Section 14.1 on page Caution: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device. Figure 4. ST7LITE49M memory map 0000h HW registers ( seeTable 3 007Fh 0080h ...

Page 18

... Dead time generation register Break enable register Reserved area (2 bytes) Interrupt software priority register 0 Interrupt software priority register 1 Interrupt software priority register 2 Interrupt software priority register 3 External interrupt control register Doc ID 13562 Rev 3 ST7LITE49M Reset status Remarks 00h R/W 00h R/W 00h R/W 00h ...

Page 19

... ST7LITE49M Table 3. Hardware register map Address Block Register label 0032h 0033h WDG WDGCR 0034h FLASH FCSR 0035h EEPROM EECSR 0036h ADCCSR 0037h ADC ADCDRH 0038h ADCDRL 0039h 003Ah MCC MCCSR 003Bh RCCR 003Ch SICSR Clock and reset 003Dh AVDTHCR 003Eh to 0047h ...

Page 20

... Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. ● Download ICP Driver code in RAM from the ICCDATA pin ● Execute ICP Driver code in RAM to program the Flash memory 20/188 Doc ID 13562 Rev 3 ST7LITE49M ...

Page 21

... ST7LITE49M Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In-application programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode) ...

Page 22

... POWER SUPPLY 22/188 PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note See Note 1 and Caution See Note 1 ST7 Doc ID 13562 Rev 3 ST7LITE49M APPLICATION BOARD APPLICATION RESET SOURCE See Note 2 APPLICATION I/O ...

Page 23

... ST7LITE49M 4.5 Memory protection There are two different types of memory protection: Read-out protection and Write/Erase Protection which can be applied individually. 4.5.1 Read-out protection Read-out protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller ...

Page 24

... Read-out protection Figure 6. EEPROM block diagram EECSR 0 ADDRESS BUS 24/188 E2LAT E2PGM ADDRESS ROW 4 DECODER DECODER 4 4 Doc ID 13562 Rev 3 ST7LITE49M HIGH VOLTAGE PUMP EEPROM MEMORY MATRIX (1 ROW = BITS) 128 128 DATA BITS MULTIPLEXER DATA LATCHES DATA BUS ...

Page 25

... ST7LITE49M 5.3 Memory access The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in different memory access modes. 5.3.1 Read operation (E2LAT=0) The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared ...

Page 26

... Row / byte ⇒ ... N Read operation impossible Programming cycle Byte 2 Byte 32 PHASE 1 PHASE 2 Writing data latches Waiting E2PGM and E2LAT to fall Doc ID 13562 Rev 3 ST7LITE49M ... 30 31 Physical Address 00h...1Fh 20h...3Fh Nx20h...Nx20h+1Fh Read operation possible Cleared by hardware ...

Page 27

... ST7LITE49M 5.6 Data EEPROM read-out protection The read-out protection is enabled through an option bit (see When this option is selected, the programs and data stored in the EEPROM memory are protected against Read-out (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the option byte, the entire Program memory and EEPROM is first automatically erased ...

Page 28

... ACCUMULATOR RESET VALUE = XXh INDEX REGISTER RESET VALUE = XXh INDEX REGISTER RESET VALUE = XXh PCL PROGRAM COUNTER CONDITION CODE REGISTER STACK POINTER Doc ID 13562 Rev 3 ST7LITE49M X = Undefined Value ...

Page 29

... ST7LITE49M 6.3.1 Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 6.3.2 Index registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register ...

Page 30

... These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See 30/188 Section 10.6: Interrupts Doc ID 13562 Rev 3 ST7LITE49M th bit of the result. for more details. ...

Page 31

... ST7LITE49M * Table 4. Interrupt software priority truth table 6.3.5 Stack pointer (SP) Reset value: 01FFh The stack pointer is a 16-bit register which is always pointing to the next free location in the stack then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware ...

Page 32

... PCL Stack Higher Address = 01FFh Stack Lower Address = 0180h 32/188 PUSH Y POP Y Interrupt Event PCH PCH PCH PCL PCL PCL PCH PCH PCH PCL PCL PCL Doc ID 13562 Rev 3 ST7LITE49M RET IRET or RSP PCH SP PCL ...

Page 33

... For compatibility reasons with the SICSR register, CR[1:0] bits are stored in the 5th and 6th position of DEE1 and DEE3 addresses. Supply, reset and clock management Conditions 25° MHz 3 25° MHz RC Doc ID 13562 Rev 3 supply voltages at 25 °C (see DD ST7LITE49M Address (1) DEE0h (CR[9:2]) (1) DEE1h (CR[1:0]) (1) DEE2h (CR[9:2]) (1) DEE3h (CR[1:0]) 33/188 ...

Page 34

... Refer to application note AN1324 for information on how to calibrate the RC frequency using an external reference signal. 7.1.2 Auto-wakeup RC oscillator The ST7LITE49M also contains an Auto-wakeup RC oscillator. This RC oscillator should be enabled to enter auto-wakeup from halt mode. The auto-wakeup (AWU) RC oscillator can also be configured as the startup clock through the CKSEL[1:0] option bits (see This is recommended for applications where very low power consumption is required ...

Page 35

... ST7LITE49M Figure 12. Clock switching Figure 13. Clock management block diagram CK2 CK1 CR9 CR8 Prescaler CLKSEL[1:0] Option bits CLKIN CLKIN CLKIN CLKIN OSC /OSC1 1-16 MHz or 32kHz OSC2 f OSC /32 DIVIDER Set RC/AWU Internal RC Poll AWU_FLAG until set Reset RC/AWU AWU RC Poll RC_FLAG until set ...

Page 36

... These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. 7.2.3 Internal RC oscillator In this mode, the tunable 1% RC oscillator is used as main clock source. The two oscillator pins have to be tied to ground. The calibration is done through the RCCR[7:0] and SICSR[6:5] registers. 36/188 Doc ID 13562 Rev 3 ST7LITE49M ...

Page 37

... ST7LITE49M Table 6. ST7 clock sources 7.3 Reset sequence manager (RSM) 7.3.1 Introduction The reset sequence manager includes three RESET sources as shown in ● External RESET source pulse ● Internal LVD RESET (low voltage detection) ● Internal WATCHDOG RESET Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. ...

Page 38

... External crystal/ceramic 32 kHz oscillator Figure 14. Reset sequence phases 38/188 Clock source Internal RC 8 MHz oscillator Internal RC 32 kHz oscillator RESET Internal reset active phase 256 or 4096 clock cycles Doc ID 13562 Rev 3 ST7LITE49M CPU clock cycle delay 4096 256 4096 4096 4096 256 Fetch vector ...

Page 39

... ST7LITE49M 7.3.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristics section for more details. ...

Page 40

... IT-(LVD) EXTERNAL RESET SOURCE RESET PIN WATCHDOG RESET 40/188 . w(RSTL)out LVD RESET RUN RUN ACTIVE PHASE t h(RSTL)in WATCHDOG UNDERFLOW Doc ID 13562 Rev 3 ST7LITE49M EXTERNAL WATCHDOG RESET RESET RUN RUN ACTIVE ACTIVE PHASE PHASE t w(RSTL)out INTERNAL RESET (256 or 4096 T VECTOR FETCH ) CPU ...

Page 41

... ST7LITE49M 7.4 System integrity management (SI) The system integrity management block contains the low voltage detector (LVD) and auxiliary voltage detector (AVD) functions managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Section 12.2.1 on page 136 7 ...

Page 42

... TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT MANAGER SICSR (RSM) 0 CR1 CR0 main supply voltage (V DD main supply DD threshold (AVDF bit is set). Doc ID 13562 Rev 3 ST7LITE49M STATUS FLAG AVD Interrupt Request WDGF 0 LVDRF AVDF AVDIE LOW VOLTAGE DETECTOR (LVD) AUXILIARY VOLTAGE DETECTOR (AVD) ) ...

Page 43

... ST7LITE49M Note: Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to 143 for more details. Figure 19. Using the AVD to monitor IT+(AVD) V IT-(AVD) V IT+(LVD) V IT-(LVD) AVDF bit ...

Page 44

... To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h. 44/188 0 0 Read/write or f /32. OSC OSC f CPU = OSC f /32) CPU = OSC CR7 CR6 CR5 Read/write Doc ID 13562 Rev 3 ST7LITE49M 0 0 MCO CR4 CR3 Chapter 0 SMS 0 CR2 7.5.3. ...

Page 45

... ST7LITE49M 7.5.3 System integrity (SI) control/status register (SICSR) Reset value: 011x 0x00 (xxh CR1 Bit 7 = Reserved, must be kept cleared Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer to Section 7 ...

Page 46

... They are set and cleared by software. They are set by hardware after a reset. Table 12. AVD threshold selection bits AVD1 AVD0 46/188 CK0 0 0 Read/write and Table 11. CK0 Doc ID 13562 Rev 3 ST7LITE49M 0 AVD1 Figure 13: Clock management block f OSC f RC/2 f RC/4 f RC/8 f RC/ Functionality Low Medium High AVD off 0 AVD0 ...

Page 47

... ST7LITE49M 7.5.5 Clock controller control/status register (CKCNTCSR) Reset value: 0000 1001 (09h Bits 7:4 = Reserved, must be kept cleared. Bit 3 = AWU_FLAG AWU selection bit This bit is set and cleared by hardware switch from AWU to RC requested 1: AWU clock activated and temporization completed Bit 2 = RC_FLAG RC selection bit This bit is set and cleared by hardware ...

Page 48

... The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. 48/188 Figure 20. Doc ID 13562 Rev 3 ST7LITE49M ...

Page 49

... ST7LITE49M Table 14. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Figure 20. Interrupt processing flowchart RESET RESTORE PC FROM STACK Level Low High PENDING Y INTERRUPT Interrupt has the same lower software priority than current one ...

Page 50

... The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details. 50/188 PENDING INTERRUPTS Different Same SOFTWARE PRIORITY HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED Figure 20. Doc ID 13562 Rev 3 ST7LITE49M ...

Page 51

... Note interrupt, that is not able to Exit from Halt mode, is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced. Table 18: ST7LITE49M interrupt Table 18: ST7LITE49M interrupt Doc ID 13562 Rev 3 mapping. mapping). When several pending ...

Page 52

... The 23. The interrupt hardware priority is given in this order from the IT0 IT1 IT2 IT2 IT3 IT4 TLI IT0 IT1 IT2 IT3 IT4 IT4 Doc ID 13562 Rev 3 ST7LITE49M SOFTWARE I1 PRIORITY LEVEL ...

Page 53

... ST7LITE49M 8.5 Description of interrupt registers 8.5.1 CPU CC register interrupt bits Reset value: 111x 1010(xAh Bits I1, I0 Software interrupt priority bits These two bits indicate the current interrupt software priority (see These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx) ...

Page 54

... Entering Halt mode Pop CC I1 Jump if I1:0 <> 11 I1:0 <> 11 Mem => CC Load Load Software trap Software NMI Wait for interrupt Doc ID 13562 Rev 3 ST7LITE49M ISPRx bits (1) I1_0 and I0_0 bits I1_1 and I0_1 bits ... I1_13 and I0_13 bits ( ...

Page 55

... ST7LITE49M Table 18. ST7LITE49M interrupt mapping Source Number block RESET TRAP 0 AWU 1 AVD Auxiliary voltage detector interrupt 2 ei0 External interrupt 0 (Port A) 3 ei1 External interrupt 1 (Port B) 4 ei2 External interrupt 2 (Port timer output compare interrupt 6 AT timer input capture interrupt AT TIMER ...

Page 56

... ISx0 56/188 IS21 IS20 IS11 Read/write External interrupt sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge Doc ID 13562 Rev 3 ST7LITE49M 0 IS10 IS01 IS00 Table 19. Table 19. Table 19. Section : External interrupt ...

Page 57

... ST7LITE49M 9 Power saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see ● Slow ● Wait (and Slow-wait) ● Active-halt ● Auto-wakeup from Halt (AWUFH) ● Halt After a reset the normal operating mode is selected by default (Run mode). This mode ...

Page 58

... The MCU will remain in Wait mode until a reset or an interrupt occurs, causing it to wake up. Refer to Figure 26 58/188 ) to the available supply voltage. CPU f OSC f CPU f OSC SMS for a description of the Wait mode flowchart. Doc ID 13562 Rev 3 ST7LITE49M /32 f OSC NORMAL RUN MODE REQUEST ...

Page 59

... ST7LITE49M Figure 26. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 9.4 Active-halt and Halt modes Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘ ...

Page 60

... This means that the device cannot spend more than a defined delay in this power saving mode. Figure 27. Active-halt timing overview [Active-halt Enabled] 1. This delay occurs only if the MCU exits Active-halt mode by means of a RESET. 60/188 Figure 28). ACTIVE RUN HALT CYCLE DELAY HALT INTERRUPT INSTRUCTION Doc ID 13562 Rev 3 ST7LITE49M Figure 28). 256 CPU RUN 1) RESET OR FETCH VECTOR ...

Page 61

... HALT instruction when Active-halt mode is disabled. The MCU can exit Halt mode on reception of either a specific interrupt (see ST7LITE49M interrupt an interrupt, the main oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see When entering Halt mode, the I bit in the CC register is forced enable interrupts ...

Page 62

... Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 18: ST7LITE49M interrupt 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. ...

Page 63

... ST7LITE49M Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference unforeseen logical condition. ● ...

Page 64

... AWU_RC to the input capture of the 8-bit Lite timer, allowing the AWU_RC Section 9.4: Active-halt and Halt t AWU HALT MODE Doc ID 13562 Rev 3 ST7LITE49M ). Its frequency is divided by AWU_RC modes). 256 t RUN MODE CPU Clear by software ...

Page 65

... AWU RC OSC Y MAIN OSC PERIPHERALS CPU I[1:0] BITS 256 CPU CLOCK CYCLE AWU RC OSC MAIN OSC PERIPHERALS CPU I[1:0] BITS FETCH RESET VECTOR OR SERVICE INTERRUPT Table 18: ST7LITE49M interrupt mapping Doc ID 13562 Rev 3 Power saving modes WATCHDOG DISABLE ON OFF 2) OFF OFF 10 RESET Y OFF ON OFF ...

Page 66

... AWUFH (Auto-wakeup from Halt) mode disabled 1: AWUFH (Auto-wakeup from Halt) mode enabled Note: Whatever the clock source, this bit should be set to enable the AWUFH mode once the HALT instruction has been executed. 66/188 Read/Write Doc ID 13562 Rev 3 ST7LITE49M 0 AWU AWUM AWUEN F ...

Page 67

... ST7LITE49M 9.5.3 AWUFH prescaler register (AWUPR) Reset value: 1111 1111 (FFh) 7 AWUPR7 AWUPR6 Bits 7:0= AWUPR[7:0] Auto-wakeup prescaler These 8 bits define the AWUPR dividing factor (see Table 21. Configuring the dividing factor AWUPR[7:0 00h 01h ... FEh FFh In AWU mode, the time during which the MCU stays in Halt mode, t equation below ...

Page 68

... External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. 68/188 Doc ID 13562 Rev 3 ST7LITE49M ...

Page 69

... ST7LITE49M Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register. ...

Page 70

... ENABLE BIT If implemented 1 0 Combinational Logic FROM OTHER BITS Note: Refer to the Port Configuration table for device specific information. Doc ID 13562 Rev 3 ST7LITE49M describes which peripheral signals can P-BUFFER V DD (see table below) PULL-UP (see table below PULL-UP PAD CONDITION ...

Page 71

... ST7LITE49M Table 24. I/O port mode options Configuration mode Floating with/without Interrupt Input Pull-up with Interrupt Output Open-drain (logic level) 1. Off means implemented not activated, On means implemented and activated. Table 25. I/O port configuration PAD PAD PAD 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status ...

Page 72

... OUTPUT floating/pull-up floating open-drain interrupt (reset state) XX Description No effect on I/O ports. External interrupts cause the device to exit from Wait No effect on I/O ports. External interrupts cause the device to exit from Halt Doc ID 13562 Rev 3 ST7LITE49M Figure 11 OUTPUT push-pull = DDR, OR Section 13.9: I/O port mode. mode. 35. ...

Page 73

... ST7LITE49M 10.6 Interrupts The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction). Table 27. Description of interrupt events Interrupt event External interrupt on selected external event See application notes AN1045 software implementation of software LCD driver 10 ...

Page 74

... Output open-drain true open-drain open-drain open-drain pull-up open-drain ST7LITE49M push-pull push-pull push-pull push-pull 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 ...

Page 75

... ST7LITE49M 11 On-chip peripherals 11.1 Watchdog timer (WDG) 11.1.1 Introduction The watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared ...

Page 76

... WDG reset immediately after waking up the microcontroller. Same behavior in Active-halt mode. 11.1.5 Interrupts None. 76/188 timing): (1)( MHz CPU min [ms] 1 127 Table 33 is due to the unknown status of the prescaler when writing to the Section 14 on page Doc ID 13562 Rev 3 ST7LITE49M max [ms] 2 128 173. ...

Page 77

... ST7LITE49M 11.1.6 Register description Control register (WDGCR) Reset value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. ...

Page 78

... Triggered by rising and falling edges – Maskable IC interrupt – Long range input capture ● Internal/external break control ● Flexible clock control ● One-pulse mode on PWM2/3 ● Force update 78/188 ) CPU Doc ID 13562 Rev 3 ST7LITE49M ...

Page 79

... ST7LITE49M Figure 37. Single timer mode (ENCNTR2=0) ATIC Edge Detection Circuit 12-Bit Autoreload register 1 Clock Control Figure 38. Dual timer mode (ENCNTR2=1) Edge Detection Circuit ATIC 12-Bit Autoreload register 1 12-Bit Autoreload register 2 Control LTIC 12-bit Input Capture PWM0 Duty Cycle Generator PWM1 Duty Cycle Generator ...

Page 80

... DCRx register must be greater than the contents of the ATR register. 80/188 Figure 37 and Figure 38). The frequency is controlled by the counter ⁄ 4096 ATR = PWM COUNTER equals 4 MHz COUNTER ⁄ ( Resolution = 1 4096 ATR Doc ID 13562 Rev 3 ST7LITE49M ) or can have two different PWM ) – the maximum value – is PWM ...

Page 81

... ST7LITE49M The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. ● Polarity inversion The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2 register is set (reset value) ...

Page 82

... OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be generated. 3 Dead time generation does not work at 1ms timebase. 82/188 ATR= FFDh FFDh FFEh FFFh FFDh [ ] × Dead time = DT 6:0 Doc ID 13562 Rev 3 ST7LITE49M FFEh FFFh FFDh Tcounter1 ≠ DTE is set and DT[6:0]=0, FFEh t ...

Page 83

... ST7LITE49M Figure 42. Dead time generation CK_CNTR1 CNTR1 PWM 0 PWM 1 PWM 0 PWM 1 In the above example, when the DTE bit is set: ● PWM goes low at DCR0 match and goes high at ATR1+Tdt ● PWM1 goes high at DCR0+Tdt and goes low at ATR match. With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are not overlapped ...

Page 84

... ATR1, ATR2, preload and active DCRx are put to their reset values. ● Counters stop counting. When the break function is deactivated after applying the break (BA bit goes from software), Timer takes the control of PWM ports. Figure 43. ST7LITE49M block diagram of break function BREAK pin BREAKEN register BREN2 Output compare mode To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers ...

Page 85

... ST7LITE49M Figure 44. Block diagram of output compare mode (single timer) DCRx PRELOAD DUTY CYCLE REG0/1/2/3 (ATCSR2) TRAN1 (ATCSR) OVF CNTR1 Input capture mode The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter CNTR1 after a rising or falling edge is detected on the ATIC pin. When an Input Capture occurs, the ICF bit is set and the ATICR register contains the value of the free running upcounter ...

Page 86

... OSC/32 8-bit Timebase Counter1 ATR1 12-bit AutoReload register f CNTR1 LTIMER f cpu 12-bit Upcounter1 OFF ATICR 12-bit Input Capture register Doc ID 13562 Rev 3 ST7LITE49M 07h 08h 09h 0Ah INTERRUPT ATICR READ 09h 04h equals 8 OSC 8 LSB bits LITE TIMER 20 12-bit ARTIMER cascaded ...

Page 87

... ST7LITE49M Since the input capture flags (ICF) for both timers (AT4 timer and LT timer) are set when signal transition occurs, software must mask one interrupt by clearing the corresponding ICIE bit before setting the ICS bit. If the ICS bit changes (from from 1 to 0), a spurious transition might occur on the Input Capture signal because of different values on LTIC and ATIC ...

Page 88

... CNTR1 LTIC LTICR ATICRH ATICRL 88/188 00h LT1 F9h 00h ATH1 & ATL1 00h LT1 0h ATH1 00h ATL1 Doc ID 13562 Rev 3 ST7LITE49M LT2 ATH2 & ATL2 LT2 ATH2 ATL2 ATICR = ATICRH[3:0] & ATICRL[7: ...

Page 89

... ST7LITE49M One-pulse mode One-pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in Dual Timer mode i.e. only for CNTR2, when the OP_EN bit in PWM3CSR register is set. One-pulse mode is activated by the external LTIC input. The active edge of the LTIC pin is selected by the OPEDGE bit in the PWM3CSR register ...

Page 90

... Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode. 90/188 OP_EN 12-bit AutoReload register 2 12-bit Active DCR2/3 000 DCR2/3 OVF ATR2 DCR2/3 OVF Doc ID 13562 Rev 3 ST7LITE49M 12-bit Upcounter 2 PWM Generation OP2/3 000 DCR2/3 ATR2 ATR2 DCR2/3 ATR2 OVF ...

Page 91

... ST7LITE49M Figure 51. Dynamic DCR2/3 update in One-pulse mode f counter2 CNTR2 LTIC FORCE2 TRAN2 DCR2/3 PWM2/3 Force update In order not to wait for the counter programmable counter which when set, make the counters start with the overflow value, i.e. FFFh. After overflow, the counters start counting from their respective auto reload register values. ...

Page 92

... No effect on AT timer AT timer halted. Event Enable Exit from flag control bit Wait OVF1 OVIE1 Yes ICF ICIE Yes OVF2 OVIE2 Yes ICIE CK1 CK0 Read / Write Doc ID 13562 Rev 3 ST7LITE49M Exit from Exit from Halt Active-halt No Yes OVF1 OVFIE1 CMPIE ...

Page 93

... ST7LITE49M Bits 4:3 = CK[1:0] Counter clock selection bits These bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. Table 37. Counter clock selection Bit 2 = OVF1 Overflow flag This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter1 CNTR1 from FFFh to ATR1 value ...

Page 94

... PWM mode disabled. PWMx output alternate function disabled (I/O pin free for general purpose I/O) 1: PWM mode enabled 94/188 =f , special care must be taken when CNTR1L values timer CPU 0 0 ATR11 Read/write ATR5 ATR4 ATR3 Read/write 0 OE2 0 Read/write Doc ID 13562 Rev 3 ST7LITE49M 8 ATR10 ATR9 ATR8 0 ATR2 ATR1 ATR0 0 OE1 0 OE0 ...

Page 95

... ST7LITE49M PWMX control status register (PWMxCSR) Reset value: 0000 0000 (00h Bits 7:4= Reserved, must be kept cleared. Bit 3 = OP_EN One-pulse mode enable bit This bit is read/write by software and cleared by hardware after a reset. This bit enables the One-pulse feature for PWM2 and PWM3 (only available for PWM3CSR) 0: One-pulse mode disable for PWM2/3 ...

Page 96

... In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see be compared with the 12-bit upcounter value. 96/188 0 0 DCR11 Read/write DCR5 DCR4 DCR3 Read/write Figure 40). In output compare mode, they define the value to Doc ID 13562 Rev 3 ST7LITE49M 8 DCR10 DCR9 DCR8 0 DCR2 DCR1 DCR0 Figure 40). ...

Page 97

... ST7LITE49M Input capture register high (ATICRH) Reset value: 0000 0000 (00h Bits 15:12 = Reserved. Input capture register low (ATICRL) Reset value: 0000 0000 (00h) 7 ICR7 ICR6 Bits 11:0 = ICR[11:0] Input capture data. This is a 12-bit register which is readable by software and cleared by hardware after a reset ...

Page 98

... PWM2/3 is generated using CNTR1. 1: PWM2/3 is generated using CNTR2. Note: Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the counter will restart from the last value. 98/188 ICS OVFIE2 OVF2 Read/write Doc ID 13562 Rev 3 ST7LITE49M 0 ENCNTR2 TRAN2 TRAN1 ...

Page 99

... ST7LITE49M Bit 1= TRAN2 Transfer enable2 bit This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2. It allows the value of the Preload DCRx registers to be transferred to the Active DCRx registers after the next overflow event. ...

Page 100

... ATR6 ATR5 ATR4 OE3 OE2 Doc ID 13562 Rev 3 ST7LITE49M DT3 DT2 DT1 CK0 OVF1 OVFIE1 CNTR1_1 CNTR1_1 CNTR1_9 CNTR1_3 CNTR1_2 CNTR1_1 ATR11 ATR10 ATR9 0 ...

Page 101

... ST7LITE49M Table 38. Register mapping and reset values (continued) Add. Register 7 (Hex) label DCR0L DCR7 001C Reset value 0 DCR1H 001D 0 Reset value DCR1L DCR7 001E Reset value 0 DCR2H 001F 0 Reset value DCR2L DCR7 0020 Reset value 0 DCR3H 0021 0 Reset value DCR3L DCR7 ...

Page 102

... INPUT CAPTURE REGISTER 102/188 LTCSR2 Timebase f LTIMER MHz f ) OSC 8 8-bit LTCSR1 ICIE ICF TB TB1IE TB1F Doc ID 13562 Rev 3 ST7LITE49M ) OSC ) OSC LTTB2 Interrupt request 0 0 TB2IE TB2F f LTIMER To 12-bit AT TImer LTTB1 INTERRUPT REQUEST LTIC INTERRUPT REQUEST ...

Page 103

... ST7LITE49M 11.3.3 Functional description Timebase counter 1 The 8-bit value of counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f counter rolls over from F9h to 00h counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR1 register ...

Page 104

... No effect on Lite timer Lite timer stops counting Enable Exit Event control from flag Bit Wait TB1F TB1IE TB2F TB2IE Yes ICF ICIE Read / Write Doc ID 13562 Rev 3 ST7LITE49M Description /32) OSC Exit Exit from from Active-halt Halt Yes TB2IE TB2F ...

Page 105

... ST7LITE49M Bit 0 = TB2F Timebase 2 Interrupt flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect Counter 2 overflow 1: A Counter 2 overflow has occurred Lite timer autoreload register (LTARR) Reset value: 0000 0000 (00h) 7 AR7 ...

Page 106

... OSC * 16000 ( MHz) OSC ICR5 ICR4 ICR3 Read only AR6 AR5 AR4 CNT6 CNT5 CNT4 Doc ID 13562 Rev 3 ST7LITE49M ICR2 ICR1 ICR0 TB2IE AR3 AR2 AR1 CNT3 CNT2 CNT1 TB2F ...

Page 107

... ST7LITE49M Table 41. Lite timer register mapping and reset values (continued) Address Register 7 label (Hex.) LTCSR1 ICIE 0F Reset value 0 LTICR ICR7 10 Reset value ICF TB TB1IE TB1F ICR6 ICR5 ICR4 Doc ID 13562 Rev 3 On-chip peripherals ICR3 ...

Page 108

... It can be connected both with a standard I 2 Fast I C bus. This selection is made by software. 108/188 protocol converter 2 C address detection Doc ID 13562 Rev 3 ST7LITE49M bus-specific 2 C mode (400 kHz bus by a data pin 2 C bus and a ...

Page 109

... ST7LITE49M Mode selection The interface can operate in the four following modes: ● Slave transmitter/receiver ● Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability ...

Page 110

... SDA or SDAI SCL or SCLI 110/188 DATA CONTROL CLOCK CONTROL CLOCK CONTROL REGISTER (CCR) CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) STATUS REGISTER 2 (SR2) Doc ID 13562 Rev 3 ST7LITE49M DATA REGISTER (DR) DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER 1 (OAR1) OWN ADDRESS REGISTER 2 (OAR2) CONTROL LOGIC INTERRUPT ...

Page 111

... ST7LITE49M 11.4.4 Functional description Refer to the CR, SR1 and SR2 registers default the I C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register. Slave mode As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register ...

Page 112

... SMBus compatibility 2 ST7 compatible with SMBus V1.1 protocol. It supports all SMBus addressing modes, SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave 2 Driver For ST7 I 112/188 C Peripheral. Doc ID 13562 Rev 3 ST7LITE49M Figure 57 Transfer sequencing ...

Page 113

... ST7LITE49M Master mode To switch from default Slave mode to Master mode a Start condition generation is needed. Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if the ITE bit is set ...

Page 114

... It is then necessary to release both lines by software. The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time. 114/188 Figure 57 Transfer sequencing EV8 master is on the first pulse of a Doc ID 13562 Rev 3 ST7LITE49M 2 C ...

Page 115

... ST7LITE49M Figure 57. Transfer sequencing 7-bit slave receiver S Address A 7-bit slave transmitter S Address A 7-bit master receiver S Address A EV5 7-bit master transmitter S Address A EV5 10-bit slave receiver S Header A 10-bit slave transmitter 10-bit master transmitter S Header A EV5 10-bit master receiver 1. S=Start Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, EVx=Event (with interrupt r if ITE=1) ...

Page 116

... C interrupts cause the device to exit from Wait mode registers are frozen interface is inactive and does not acknowledge data on the bus. The Halt mode” capability. ITE (1) Bus error event Doc ID 13562 Rev 3 ST7LITE49M 2 C interface 2 C interface. INTERRUPT EVF Enable Exit Event control ...

Page 117

... ST7LITE49M 11.4.7 Register description control register (I2CCR) Reset value: 0000 0000 (00h Bits 7:6 = Reserved. Forced hardware. Bit Peripheral Enable bit This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Note: When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. ...

Page 118

... This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 58 SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See Figure 57) is detected. 118/188 for the relationship between the events and the interrupt. Doc ID 13562 Rev 3 ST7LITE49M ...

Page 119

... ST7LITE49M status register 1 (I2CSR1) Reset value: 0000 0000 (00h) 7 EVF ADD10 Bit 7 = EVF Event flag This bit is set by hardware as soon as an event occurs cleared by software reading SR2 register in case of error event or as described in hardware when the interface is disabled (PE=0). ...

Page 120

... START=1). An interrupt is generated if ITE= cleared by software reading SR1 register followed by writing the address byte in DR register also cleared by hardware when the interface is disabled (PE=0 Start condition 1: Start condition generated 120/188 57). BTF is cleared by reading SR1 register followed by writing the Doc ID 13562 Rev 3 ST7LITE49M ...

Page 121

... ST7LITE49M status register 2 (I2CSR2) Reset value: 0000 0000 (00h Bits 7:5 = Reserved. Forced hardware. Bit Acknowledge failure bit This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE= cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0) ...

Page 122

... DR register. 122/188 CC5 CC4 Read / Write 2 C mode bit 2 C mode SCL assumes no load on SCL and SDA lines. SCL D5 D4 Read / Write Doc ID 13562 Rev 3 ST7LITE49M CC3 CC2 CC1 2 ) depending on the I C mode. They are not CC0 0 D0 ...

Page 123

... ST7LITE49M own address register (I2COAR1) Reset value: 0000 0000 (00h) 7 ADD7 ADD6 ● In 7-bit addressing mode Bits 7:1 = ADD[7:1] Interface address. These bits define the I interface. They are not cleared when the interface is disabled (PE=0). Bit 0 = ADD0 Address direction bit. This bit is don’t care, the interface acknowledges either not cleared when the interface is disabled (PE=0) ...

Page 124

... ADD10 TRA BUSY CC6 CC5 CC4 ADD6 ADD5 ADD4 FR0 Doc ID 13562 Rev 3 ST7LITE49M START ACK STOP BTF ADSL M/ STOPF ARLO BERR CC3 CC2 CC1 ADD3 ADD2 ADD1 ...

Page 125

... ST7LITE49M 11.5 10-bit A/D converter (ADC) 11.5.1 Introduction The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources. ...

Page 126

... ADC ANALOG MUX ADCDRH D9 D8 ADCDRL ) is greater than V (high-level voltage reference) then the AIN DDA ) is lower than V (low-level voltage reference) then the AIN SSA Doc ID 13562 Rev 3 ST7LITE49M 1 f ADC 0 bit ADCCSR CH1 CH0 HOLD CONTROL ANALOG TO DIGITAL CONVERTER C ADC D7 D6 ...

Page 127

... ST7LITE49M Configuring the A/D conversion The analog input ports must be configured as input, no pull-up, no interrupt (see I/O ports). Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. To assign the analog channel to convert, select the CH[2:0] bits in the ADCCSR register. ...

Page 128

... The number of channels is device dependent. Refer to the device pinout description. 128/188 ADON 0 Read/write (1) CH3 AIN0 0 AIN1 0 AIN2 0 AIN3 0 AIN4 0 AIN5 0 AIN6 0 AIN7 0 AIN8 1 AIN9 1 Doc ID 13562 Rev 3 ST7LITE49M CH3 CH2 CH1 CH2 CH1 CH0 ...

Page 129

... ST7LITE49M Data register high (ADCDRH) Reset value: xxxx xxxx (xxh Bits 7:0 = D[9:2] MSB of analog converted value ADC control/data register low (ADCDRL) Reset value: 0000 00xx (0xh Bits 7:4 = Reserved. Forced by hardware to 0. Bit 3 = SLOW Slow mode bit This bit is set and cleared by software used together with the SPEED bit in the ADCCSR register to configure the ADC clock speed as shown on the table below ...

Page 130

... A,#$55 ld A,$10 00..FF ld A,$1000 0000..FFFF ld A,(X) 00..FF ld A,($10,X) 00..1FE ld A,($1000,X) 0000..FFFF ld A,[$10] 00..FF ld A,[$10.w] 0000..FFFF ld A,([$10],X) 00..1FE Doc ID 13562 Rev 3 ST7LITE49M Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5 Pointer Pointer Length address size (bytes ...

Page 131

... ST7LITE49M Table 51. ST7 addressing mode overview (continued) Mode Long Indirect Indexed Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Relative Bit Indirect Relative 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. 12.1.1 Inherent mode All Inherent instructions consist of a single byte ...

Page 132

... The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE addressing space. 132/188 Instruction MUL SWAP LD CP BCP Doc ID 13562 Rev 3 ST7LITE49M Function Byte multiplication Shift and rotate operations Swap nibbles Function Load Compare Bit compare Logical operations ...

Page 133

... ST7LITE49M Indexed mode (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect modes (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two ...

Page 134

... INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SWAP CALL, JP JRxx CALLR Doc ID 13562 Rev 3 ST7LITE49M Function Clear Increment/decrement Test negative or zero complement Bit operations Bit test and jump operations Shift and rotate operations Swap nibbles Call or jump subroutine ...

Page 135

... ST7LITE49M 12.2 Instruction groups The ST7 family devices use an instruction set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Table 56. ST7 instruction set Instructions Load and Transfer Stack operation Increment/decrement Compare and tests Logical operations Bit operation ...

Page 136

... Byte, #3, Jmp1 M btjt Byte, #3, Jmp1 M reg, M tst(Reg - M) reg A = FFH-A reg, M dec Y reg, M Pop CC inc X reg [TBL.w] jrf * Doc ID 13562 Rev 3 ST7LITE49M Src ...

Page 137

... ST7LITE49M Table 57. Illegal opcode detection (continued) Mnemo Description JRPL Jump (plus) JREQ Jump (equal) JRNE Jump (not equal) JRC Jump JRNC Jump JRULT Jump JRUGE Jump JRUGT Jump JRULE Jump ...

Page 138

... Instruction set Table 57. Illegal opcode detection (continued) Mnemo Description WFI Wait for interrupt XOR Exclusive OR 138/188 Function/Example Dst XOR M A Doc ID 13562 Rev 3 ST7LITE49M Src ...

Page 139

... ST7LITE49M 13 Electrical characteristics 13.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 13.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range) ...

Page 140

... Electrostatic discharge voltage (Human body model) Electrostatic discharge voltage (Charge device model according to their reset configuration. >V while a negative injection is induced Doc ID 13562 Rev 3 ST7LITE49M ST7 PIN Maximum value 7.0 (1)( see Section 13.8.3 on page 157 could damage the device if an unintentional maximum is respected ...

Page 141

... ST7LITE49M Table 59. Current characteristics Symbol I VDD I VSS I IO (2)(3) I INJ(PIN) ΣI (2) INJ(PIN) 1. All power (V ) and ground ( must never be exceeded. This is implicitly insured if V INJ(PIN) cannot be respected, the injection current must be limited externally to the I injection is induced by V pads, there is no positive injection current, and the corresponding V 3 ...

Page 142

... MHz max. 3.3 ≤ 5 < 3 supply voltage DD FUNCTIONALITY GUARANTEED IN THIS AREA (UNLESS OTHERWISE STATED IN THE TABLES OF PARAMETRIC DATA) SUPPLY VOLTAGE [V] 5.5 4.0 4.5 5.0 Conditions Min Typ 3.9 4.2 3.2 3.5 2.5 2.7 3.7 4.0 3.0 3.3 2.4 2.6 -V 150 IT- (LVD) (LVD ST7LITE49M Max Unit 5.5 V 5.5 MHz Max Unit 4.5 3.8 3.0 V 4.3 3.6 2.9 mV μs/V μA 140 ...

Page 143

... ST7LITE49M 2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application recommended to pull V circuit example in 13.3.3 Auxiliary voltage detector (AVD) thresholds T = -40 to 125 °C unless otherwise specified A , Table 63. Operating characteristics with AVD Symbol 1=>0 AVDF flag toggle ...

Page 144

... DD (1) RCCR = RCCR1 ° 3 Doc ID 13562 Rev 3 pins as close as possible to the ST7 SS Min Typ 5 ( (2) -2 -2.5 (2) -3 (2) -4 (2) ( Min Typ 4.3 , 7.84 8 ST7LITE49M Max Unit MHz 8.16 kHz 2.5 % μs Max Unit MHz 8.16 ...

Page 145

... ST7LITE49M Table 66. Internal RC oscillator characteristics (3.3 V calibration) Symbol Parameter Accuracy of internal ACC RC oscillator with RC 1) RCCR=RCCR1 RC oscillator setup t su(RC) time 1. See Section 7.1.1: Internal RC oscillator 2. Tested in production at 3.3 V only Figure 63. Frequency vs voltage at four different ambient temperatures ( Figure 64. Frequency vs voltage at four different ambient temperatures (RC at 3.3 V) ...

Page 146

... Figure 65. Accuracy voltage at 4 different ambient temperatures ( Figure 66. Accuracy voltage at 4 different ambient temperatures (RC at 3.3 V) 146/188 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 VDD (V) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 VDD (V) Doc ID 13562 Rev 3 ST7LITE49M R C5V% @-40 °C R C5V% @25 °C R C5V% @85 °C R C5V% @12 5 °C RC 3.3V °C RC 3.3C °C RC 3.3V%@ 85 °C RC 3.3V%@ 125 °C ...

Page 147

... ST7LITE49M 13.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for Halt mode for which the clock is stopped) ...

Page 148

... Figure 69. Typical I 148/188 in Run mode vs CPU 6.0 2MHz 5.0 4MHz 4.0 8MHz 3.0 2.0 1.0 0.0 Vdd [V] in WFI vs CPU 2MH z 2.5 4MH z 2 8MH z 1.5 1 0.5 0 Vdd [V] in slow mode vs CPU 2MHz 4MHz 0 .5 8MHz Vdd [V] Doc ID 13562 Rev 3 ST7LITE49M ...

Page 149

... ST7LITE49M Figure 70. Typical I Figure 71. Typical I in Slow-wait mode vs CPU 2 MHz 0.6 0.5 4 MHz 0.4 8 MHz 0.3 0.2 0.1 0 Vdd [V] vs. temperature and -40 °C 25°C 8 5°C Temp[°C] Doc ID 13562 Rev 3 Electrical characteristics = 8 MHz CPU RUN WFI SLOW SLOW-WAIT 125° ...

Page 150

... A interface meets the electrical and timing 2 C communication protocol. Parameter Conditions f =4 MHz to 8 MHz, CPU V = 2 Doc ID 13562 Rev 3 ST7LITE49M Conditions =3 MHz V CPU DD =5 MHz V CPU DD =3 MHz ...

Page 151

... ST7LITE49M Table 70. SCL frequency (multimaster I f CPU f SCL =3.3 kΩ R =4.7 kΩ 400 NA NA 300 NA NA 200 84h 84h 100 11h 11h 50 25h 25h 20 61h 61h External pull-up resistance For fast mode speeds, achieved speed can have ±5% tolerance. For other speed ranges, achieved speed can have ±2% tolerance ...

Page 152

... Doc ID 13562 Rev 3 Conditions Min Typ 0.7xV DD V 0.3xV SS see Figure 72 15 ≤ V ≤ w(OSC1H or CLKINH)) w(OSC1L or CLKINL) Not connected internally f OSC I L ST7xxx Min Typ Max 16 32 ST7LITE49M Max Unit μA ±1 Unit 64 kHz 50 µs ...

Page 153

... ST7LITE49M 13.6.2 Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with ten different crystal/ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time ...

Page 154

... Electrical characteristics Figure 73. Typical application with a crystal or ceramic resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS 154/188 Resonator Doc ID 13562 Rev 3 ST7LITE49M OSC1 ST7LITE49M OSC2 OSC ...

Page 155

... ST7LITE49M 13.7 Memory characteristics T = -40 °C to 125 °C, unless otherwise specified. A Table 76. RAM and hardware registers characteristics Symbol V Data retention mode RM 1. Minimum V supply voltage without losing data stored in RAM (in Halt mode or under reset hardware registers (only in Halt mode). Guaranteed by construction, not tested in production. ...

Page 156

... Fast transient voltage burst limits applied through 100 FFTB pins to induce a functional disturbance 156/188 Parameter and Doc ID 13562 Rev 3 ST7LITE49M and V DD Level/ Conditions = =+25 ° MHz A OSC conforms to IEC 1000-4 =+25 ° MHz A ...

Page 157

... ST7LITE49M 13.8.2 EMI (electromagnetic interference) Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. ...

Page 158

... IN DD Floating input mode Between 10% and 90% Figure 74). Static peak current value taken at a fixed V Doc ID 13562 Rev 3 ST7LITE49M Conditions = +125 ° and T unless otherwise specified. OSC A Min Typ Max V - 0.3 0. 400 ± ...

Page 159

... ST7LITE49M Figure 74. Two typical applications with unused I/O pin kΩ 1. During normal operation the ICCCLK pin must be pulled-up, internally or externally (external pull- kΩ mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. 2. I/O can be left unconnected configured as output ( the software. This has the advantage of greater EMC robustness and lower cost ...

Page 160

... I 3. Not tested in production, based on characterization results. 160/188 , f DD CPU Conditions 79) 82) 90) and Figure 81) 89) 77) 80) 88) . VSS . VDD Doc ID 13562 Rev 3 ST7LITE49M , and T unless otherwise specified. A Min Max I =+5 mA, IO 1.0 ≤125 ° =+2 mA, IO 0.4 ≤ 125 ° =+20 mA ...

Page 161

... ST7LITE49M Figure 77. Typical V Figure 78. Typical V Figure 79. Typical 2.4 V (standard 1400 -40°C 1200 25°C 85°C 1000 125°C 800 600 400 200 Iload [mA (standard 1400 -40°C 1200 25°C 1000 85°C 125°C 800 600 400 200 ...

Page 162

... Iload [mA (high sink 900 -40°C 800 25°C 700 85°C 600 125°C 500 400 300 200 100 Iload [mA] Doc ID 13562 Rev 3 ST7LITE49M ...

Page 163

... ST7LITE49M Figure 83. Typical V 490 440 390 340 290 240 190 140 Figure 84. Typical V 1540 1340 1140 940 740 540 340 140 2.4 2.6 2.8 Figure 85. Typical V 120 110 100 vs (standard 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 Vdd [V] vs (standard ...

Page 164

... 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 Vdd [ 2.4 V (high sink 800 -40°C 700 25°C 600 85°C 500 125°C 400 300 200 100 0 2 Iload[mA] Doc ID 13562 Rev 3 ST7LITE49M -40°C 25°C 85°C 125°C 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 -40°C 25°C 85°C 125°C 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 4 ...

Page 165

... ST7LITE49M Figure 89. Typical V Figure 90. Typical (high sink 1800 -40°C 1600 25°C 1400 85°C 1200 125°C 1000 800 600 400 200 Iload[mA (high sink 4500 -40°C 4000 25°C 3500 85° ...

Page 166

... Iload[mA (standard 4500 -40°C 4000 25°C 3500 85°C 3000 125°C 2500 2000 1500 1000 500 Iload[mA] Doc ID 13562 Rev 3 ST7LITE49M ...

Page 167

... ST7LITE49M Figure 94. Typical V Figure 95. Typical (high sink 800 700 600 500 400 300 200 100 0 2.4 2.8 3.2 3.6 4 Vdd [ (high sink 1800 1600 1400 1200 1000 800 600 400 200 0 2.6 3 3.4 3.8 4.2 Vdd [V] ...

Page 168

... Internal reset sources (4) . VSS can be ignored. h(RSTL)in Doc ID 13562 Rev 3 Min Typ V - 0.3 0. 200 = ( ( 200 Section Table 59. on page 141 ST7LITE49M Max Unit kΩ μs μs ns and the ILmax ...

Page 169

... ST7LITE49M Figure 96. RESET pin protection when LVD is enabled Required EXTERNAL RESET 0.01μF 1. The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog) ...

Page 170

... CPU ADC = 25 °C and 2 2.7 V operating range is 1 MHz The first conversion after the enable is then always LOAD Doc ID 13562 Rev 3 ST7LITE49M INTERNAL RESET WATCHDOG PULSE GENERATOR ILLEGAL OPCODE 168. Otherwise the reset will not be , and T unless otherwise specified. ...

Page 171

... ST7LITE49M Figure 98. Typical application with ADC R AIN V AIN Table 87. ADC accuracy with V Symbol ( Total unadjusted error Differential linearity error Integral linearity error L 1. Data based on characterization results over the whole temperature range. Table 88. ADC accuracy with V ...

Page 172

... LSB IDEAL 1021 1022 1023 1024 Doc ID 13562 Rev 3 ST7LITE49M (1) Example of an actual transfer curve E G (2) The ideal transfer curve (3) End point correlation line ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one ...

Page 173

... ST7LITE49M 14 Device configuration and ordering information This device is available for production in user programmable version (Flash). ST7LITE49M XFlash devices are shipped to customers with a default program memory content (FFh). 14.1 Option bytes The two option bytes allow the hardware configuration of the microcontroller to be selected. ...

Page 174

... OPT 3:2 = SEC[1:0] Sector 0 size definition These option bits indicate the size of sector 0 according to 174/188 LP 1~2 MHz MP 2~4 MHz MS 4~8 MHz HS 8~16 MHz VLP 32.768 kHz Reserved External clock on PB1 Section 7.3). Doc ID 13562 Rev 3 ST7LITE49M (1) OSCRANGE ...

Page 175

... ST7LITE49M Table 93. Configuration of sector size Sector 0 Size 0. Bit 1 = FMP_R Read-out protection Read-out protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first, and the device can be reprogrammed ...

Page 176

... Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 176/188 ST7 FLI49M K Doc ID 13562 Rev 3 ST7LITE49M ...

Page 177

... Order codes for development and programming tools Table 94 below lists the ordering codes for the ST7LITE49M development and programming tools. For additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu. Table 94. ...

Page 178

... An introduction to sensorless brushless DC motor drive applications with the ST72141 AN1148 Using the ST7263 for designing a USB mouse AN1149 Handling Suspend mode on a USB mouse AN1180 Using the ST7263 kit to implement a USB game pad 178/188 Description Application examples Example drivers Doc ID 13562 Rev 3 ST7LITE49M ...

Page 179

... ST7LITE49M Table 95. ST7 application notes (continued) Identification AN1276 BLDC motor start routine for the ST72141 microcontroller AN1321 Using the ST72141 motor control MCU in Sensor mode AN1325 Using the ST7 USB low-speed firmware V4.x AN1445 Emulated 16-bit slave SPI AN1475 Developing an ST7265X mass storage application ...

Page 180

... In-application programming (IAP) drivers for ST7 HD Flash or XFlash MCUs AN1577 Device firmware upgrade (DFU) Implementation for ST7 USB applications AN1601 Software implementation for ST7DALI-EVAL AN1603 Using the ST7 USB device firmware upgrade development kit (DFU-DK) 180/188 Description Programming and tools Doc ID 13562 Rev 3 ST7LITE49M supply DDF ...

Page 181

... ST7LITE49M Table 95. ST7 application notes (continued) Identification AN1635 ST7 customer ROM code release information AN1754 Data logging program for testing ST7 applications via ICC AN1796 Field updates for Flash memory based ST7 applications using a PC comm port AN1900 Hardware implementation for ST7DALI-EVAL ...

Page 182

... Doc ID 13562 Rev (1) inches Min Typ 0.1402 0.1480 0.0201 0.1201 0.1402 0.0142 0.0181 0.0299 0.0402 0.0079 0.0098 1.0799 0.3902 0.4098 0.3000 0.3500 0.0701 0.4000 ST7LITE49M Max 0.2000 0.1799 0.0228 0.0551 0.0142 1.1201 0.4350 0.3701 0.5000 0.0551 ...

Page 183

... ST7LITE49M Table 96. 32-pin plastic dual in-line package, shrink 400-mil width, (mechanical data (continued) Dim Values in inches are converted from mm and rounded to 4 decimal digits. Figure 102. 32-pin low profile quad flat package (7x7), package outline Table 97. 32-pin low profile quad flat package (7x7), package mechanical data Dim ...

Page 184

... INT ports used in the application. 184/188 mm Min Typ Max 1.00 Number of pins Ratings (junction to ambient) Maximum junction (1) temperature (2) Power dissipation xV ) and PORT Doc ID 13562 Rev 3 ST7LITE49M (1) inches Min Typ 0.0394 32 Value LQFP32 55 SDIP32 58 150 TBD = ( thJA =P ...

Page 185

... ST7LITE49M 16 Revision history Table 99. Document revision history Date 01-Jun-2007 13-July-2007 Revision 1 Initial release. Document reformatted and status updated to Full Datasheet. Table 5. EEPROM register mapping and reset values removed. Section 7.2.3: Internal RC oscillator threshold selection register AVD[1:0] added. Table 62: Operating characteristics with I typical and maximum values updated, and note removed; ...

Page 186

... CPU clock cycle”) Modifed Section 7.5.2 on page 44 EEPROM) Added Table 12: AVD threshold selection bits on page 46 Added Section 7.5.3 on page 45 Table 18: ST7LITE49M interrupt mapping on page 55 In Section 11.2.3: Functional description on page mode section and One-pulse mode Modified Figure 45: Block diagram of input capture mode ...

Page 187

... ST7LITE49M Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...