ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 45

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

ST7LITE49M
7.5.3
System integrity (SI) control/status register (SICSR)
Reset value: 011x 0x00 (xxh)
Bit 7 = Reserved, must be kept cleared
Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits
Bit 4 = WDGRF Watchdog reset flag
This bit indicates that the last reset was generated by the watchdog peripheral. It is set by
hardware (watchdog reset) and cleared by software (writing zero) or an LVD reset (to ensure
a stable cleared state of the WDGRF flag when CPU starts). The WDGRF and the LVDRF
flags areis used to select the reset source (see
page
Table 10.
Bit 3 = Reserved, must be kept cleared
Bit 2 = LVDRF LVD reset flag
Bit 1 = AVDF Voltage detector flag
0
7
These bits, as well as CR[9:2] bits in the RCCR register must be written immediately
after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer
to
This bit indicates that the last reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled
by option byte, the LVDRF bit value is undefined.
The LVDRF flag is not cleared when another RESET type occurs (external or
watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can
not.
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt
request is generated when the AVDF bit is set. Refer to
additional details.
0: V
1: V
45).
Section 7.1.1: Internal RC oscillator on page
DD
DD
CR1
over AVD threshold
under AVD threshold
Reset source selection
External RESET pin
CR0
RESET source
Watchdog
LVD
Doc ID 13562 Rev 3
WDGRF
Read/write
Table 10: Reset source selection on
0
Supply, reset and clock management
33.
LVDRF
Figure 19
LVDRF
0
0
1
and to
AVDF
Section
WDGRF
0
1
X
AVDIE
0
45/188
for