ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 137

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

ST7LITE49M
Table 57.
Mnemo
JRUGE
JRUGT
JRULE
JRULT
SWAP
PUSH
JREQ
JRNE
JRNC
TRAP
JRPL
NEG
NOP
RRC
MUL
POP
RCF
RSP
SBC
SRA
SUB
JRC
RET
RLC
SCF
SRL
TNZ
RIM
SLA
SIM
SLL
OR
LD
Jump if Z = 0 (not equal)
Jump if Z = 1 (equal)
Shift right arithmetic
Push onto the stack
Illegal opcode detection (continued)
Jump if N = 0 (plus)
Reset stack pointer
Negate (2's compl)
Jump if (C + Z = 0)
Jump if (C + Z = 1)
Pop from the stack
Subtract with carry
Test for neg & zero
Subroutine Return
Rotate right true C
Shift left arithmetic
Disable interrupts
Enable Interrupts
Rotate left true C
Reset carry flag
Shift right logic
SWAP nibbles
No Operation
OR operation
Set carry flag
Shift left logic
Jump if C = 1
Jump if C = 0
Jump if C = 1
Jump if C = 0
Description
Subtraction
S/W trap
Multiply
Load
Dst[7..4]<=>Dst[3..0]
Function/Example
Jmp if unsigned >=
Dst7 => Dst => C
S = Max allowed
C <= Dst <= C
C => Dst => C
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
A = A - M - C
S/W interrupt
Unsigned <=
Unsigned <
Unsigned >
X,A = X * A
dst <= src
A = A + M
A = A - M
neg $10
pop reg
pop CC
tnz lbl1
N = 0 ?
C = 1 ?
C = 0 ?
Z = 1 ?
Z = 0 ?
push Y
C = 0
C = 1
I = 0
I = 1
Doc ID 13562 Rev 3
A, X, Y
reg, M
reg, M
reg, M
reg, M
reg, M
reg, M
reg, M
reg, M
reg, M
Dst
reg
CC
M
A
A
A
reg, CC
X, Y, A
M, reg
Src
M
M
M
M
M
H
H
0
0
1
1
I
I
Instruction set
N
N
N
N
N
N
N
N
N
N
N
N
N
N
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
137/188
C
C
C
C
C
C
C
C
C
C
C
0
0
1