ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 106

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

On-chip peripherals
Note:
Table 41.
106/188
Address
(Hex.)
0C
0D
0E
Bit 6 = ICF Input capture flag
After an MCU reset, software must initialize the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection bit
Bit 4 = TB1IE Timebase Interrupt enable bit
Bit 3 = TB1F Timebase Interrupt flag
Bits 2:0 = Reserved, must be kept cleared.
Lite timer input capture register (LTICR)
Reset value: 0000 0000 (00h)
Bits 7:0 = ICR[7:0] Input capture value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in the
LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling
edge occurs on the LTIC pin.
Lite timer register mapping and reset values
Reset value
Reset value
Reset value
Register
LTCSR2
LTCNTR
LTARR
label
ICR7
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No Input Capture
1: An Input Capture has occurred
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
7
CNT7
AR7
ICR6
7
0
0
0
CNT6
AR6
6
0
0
0
ICR5
OSC
OSC
Doc ID 13562 Rev 3
* 8000 (1 ms @ 8 MHz)
* 16000 (2 ms @ 8 MHz)
CNT5
AR5
5
0
0
0
ICR4
Read only
CNT4
AR4
4
0
0
0
ICR3
CNT3
AR3
3
0
0
0
ICR2
CNT2
AR2
2
0
0
0
ICR1
TB2IE
CNT1
AR1
1
0
0
0
ST7LITE49M
ICR0
CNT0
TB2F
AR0
0
0
0
0
0