ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 126

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

On-chip peripherals
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Figure 59. ADC block diagram
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (V
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (V
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics section.
R
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the alloted time.
AIN
AIN0
AIN1
AINx
is the maximum recommended impedance for an analog input signal. If the impedance
f
CPU
ANALOG
DIV 2
MUX
AIN
AIN
EOC SPEED ADON
) is greater than V
) is lower than V
4
ADCDRH
0
1
Doc ID 13562 Rev 3
R
ADC
DIV 4
0
ADCDRL
CH3
SSA
D9
DDA
(low-level voltage reference) then the
CH2
D8
(high-level voltage reference) then the
SLOW
1
bit
0
CH1
D7
HOLD CONTROL
0
CH0
D6
0
f
C
ADC
ADC
D5
ADCCSR
0
D4
0
ANALOG TO DIGITAL
D3
SLOW
CONVERTER
D2
0
ST7LITE49M
D1
D0