ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 84

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

On-chip peripherals
Note:
84/188
1
2
When a break function is activated (BA bit =1 and BREN1/BREN2 =1):
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When the break function is deactivated after applying the break (BA bit goes from 1 to 0 by
software), Timer takes the control of PWM ports.
Figure 43. ST7LITE49M block diagram of break function
Output compare mode
To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers.
When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and
DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is
generated if the CMPIE bit is set.
In Single Timer mode the output compare function is performed only on CNTR1. The
difference between both the modes is that, in Single timer mode, CNTR1 can be compared
with any of the four DCR registers, and in Dual timer mode, CNTR1 is compared with DCR0
or DCR1 and CNTR2 is compared with DCR2 or DCR3.
The output compare function is only available for DCRx values other than 0 (reset value).
Duty cycle registers are buffered internally. The CPU writes in Preload duty cycle registers
and these values are transferred in Active duty cycle registers after an overflow event if the
corresponding transfer bit (TRANx bit) is set. Output compare is done by comparing these
active DCRx values with the counters.
The break pattern (PWM[3:0] bits in the BREAKCR) is forced directly on the PWMx
output pins if respective OEx is set. (after the inverter).
The 12-bit PWM counter CNTR1 is put to its reset value, i.e. 00h (if BREN1 = 1).
The 12-bit PWM counter CNTR2 is put to its reset value,i.e. 00h (if BREN2 = 1).
ATR1, ATR2, preload and active DCRx are put to their reset values.
Counters stop counting.
BREAK pin
BREAKEN register
BREN2
BRSEL
BREN1
Level
Selection
BREDGE
BA
BREAKCR register
Doc ID 13562 Rev 3
BPEN
ENCNTR2 bit
PWM3
BREAKCR register
PWM2
PWM0/1 Break Enable
PWM2/3 Break Enable
PWM3
PWM0
PWM2
PWM1
PWM1
PWM0
(Inverters)
OEx
ST7LITE49M
PWM0
PWM1
PWM2
PWM3