TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 122

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Match with TREG4
Match with TREG5
TREG4
(Value to be compared)
Register buffer
Figure 3.8.10 Programmable Pulse Generation (PPG) Output Waveforms
Match with TREG4
(Interrupt INTTR4)
Match with TREG5
(Interrupt INTTR5)
TO4 pin
c.
16-bit programmable pulse generation (PPG) output mode
output pulse may be either low-active or high-active.
output each time the 8-bit up counter (UC4) matches the timer registers TREG4
and TREG5. However, the following conditions must be satisfied:
buffer 4 will be shifted into TREG4 on finding a match with TREG5. This feature
makes the handling of low duty waves easy.
Square wave pulse can be generated at any frequency and duty by timer 4. The
Timer 4 outputs a pulse to the TO4 pin.
In this mode, a programmable square wave is generated by inverting the timer
When the double buffer of TREG4 is enabled in this mode, the value of register
(Set value of TREG4) < (Set value of TREG5)
Figure 3.8.11 Operation of Register Buffer
Up counter = Q
93CS20-120
Q
1
1
Q
2
Shift into TREG5
Up counter = Q
Q
2
Write into TREG4
2
Q
TMP93CS20
3
2004-02-10