TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 134

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Figure 3.8.19 Programmable Pulse Generation (PPG) Output Waveforms
Match with TREG8
Match with TREG9
Register buffer
TREG8
(Value to be compared)
buffer 8 will be shifted into TREG8 on finding a match with TREG9. This feature
makes the handling of low duty waves easy.
c.
Match with TREG8
(Interrupt INTTR8)
Match with TREG9
(Interrupt INTTR9)
TO8 pin
When the double buffer of TREG8 is enabled in this mode, the value of register
16-bit programmable pulse generation (PPG) output mode
enabled by the match of the up counter UC8 with either of the timer registers
TREG8 or 9. TFF8 is also output to TO8. In this mode, the following conditions
must be satisfied:
Square wave pulse can be generated at any frequency and duty by timer 8.
The output pulse may be either low-active or high-active.
The PPG mode is obtained by inversion of the timer flip-flop TFF8 that is
(Set value of TREG8) < (Set value of TREG9)
Figure 3.8.20 Operation of Register Buffer
Up counter = Q
93CS20-132
Q
1
1
Q
2
Shift into TREG9
Up counter = Q
Q
2
2
TMP93CS20
Write into TREG8
2004-02-10
Q
3