TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 26

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

INT4, INT6, INT8, INTA, INTKEY
INT1 to INT4, INT7 to INTB
Figure 3.3.6 Timing Chart for Releasing the Halt State by Interrupt in RUN/IDLE2 Modes
(Falling edge)
(Rising edge)
AD0 to AD15
(3) Operation
INT0 (Level)
Internal INT
A0 to A23
1.
2.
CLK
ALE
NMI
WR
RD
X1
RUN mode
a HALT instruction is executed. Only the CPU stops executing further
instructions.
signal.
(See Table 3.3.6 “Halt Release Sources and Halt Release Operations”.)
RUN or IDLE2 modes.
IDLE2 mode
I/O devices, and the CPU stops executing the current instruction. In the IDLE2
mode, the halt state is released by an interrupt with the same timing as in the
RUN mode. The IDLE2 mode is released by external or internal interrupts, except
for INTWDT and INTAD interrupts. (See Table 3.3.6 “Halt Release Sources and
Halt Release Operations”.)
halt status, to prevent the watchdog timer interrupt from occurring just after
release of the HALT mode.
In the RUN mode, the system clock in the MCU continues to operate even after
In the halt state, an interrupt request is accepted on the falling edge of the CLK
Release of the RUN mode is executed by the external or internal interrupts.
Figure 3.3.6 shows the timing for releasing the halt state by interrupts in the
In the IDLE2 mode, the system clock signal is supplied only to specific internal
In the IDLE2 mode, the watchdog timer should be disabled before entering the
Address
Data
93CS20-24
Address
RUN or IDLE2
modes
Address
TMP93CS20
2004-02-10
Data