TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 245

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

T16CR
TREG6L
TREG6H
TREG7L
TREG7H
CAP6L
CAP6H
T6MOD
T6FFCR
Symbol
16-bit
timer
control
16-bit
timer
register 6
low
16-bit
timer
register 6
high
16-bit
timer
register 7
low
16-bit
timer
register 7
high
Capture
register 6
low
Capture
register 6
high
16-bit
timer 6
source
CLK and
mode
16-bit
timer 6
flip-flop
control
Name
Timer control (3/5)
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
RMW)
RMW)
RMW)
RMW)
3AH
3BH
3CH
3DH
3EH
3BH
3CH
36H
37H
Warm-up
timer
control
QCU
R/W
7
0
6
93CS20-243
0: Soft-
1: Don’t
Prescaler and timer
run/stop control
0: Stop and clear
1: Run (Count up)
CAP6IN
TARUN
capture
care
W
5
0
1
−
0
Write “0”.
T8RUN
4
0
−
0
−
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Write “0”.
R/W
W
W
W
W
R
R
−
−
−
−
−
−
TFF6 invert trigger
0: Trigger disable
1: Trigger enable
Inverted
when the
UC value
matches
TREG7
Double
buffer of
TREGA
DBAEN
EQ7T6
3
0
−
0
0
R/W
Double
buffer of
TREG8
1: UC6
Inverted
when the
UC value
matches
TREG6
DB8EN
EQ6T6
clear
enable
CLE
R/W
2
0
0
0
Double buffer
0: Disable
1: Enable
Double
buffer of
TREG6
T6CLK1
Source clock
00: TI6 input
01: φT1
10: φT4
11: φT16
00: Invert TFF6
01: Set TFF6
10: Clear TFF6
11: Don’t care
TFF6C1
DB6EN
1
0
0
1
TMP93CS20
2004-02-10
W
Double
buffer of
TREG4
T6CLK0
TFF6C0
DB4EN
0
0
0
1