TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 169

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Protocol
1.
2.
3.
4.
5.
6.
Select the 9-bit UART mode for the master and slave controllers.
Set SC0MOD<WU> bit of each slave controller to 1 to enable data receiving.
The master controller transmits one-frame data including the 8-bit select code for
the slave controllers. The MSB (Bit8)<TB8> is set to 1.
Each slave controller receives the above frame, and clears WU bit to 0 if the above
select code matches its own select code.
The master controller transmits data to the specified slave controller whose
SC0MOD<WU> bit is cleared to 0. The MSB (Bit8)<TB8> is cleared to 0.
The other slave controllers (with the <WU> bit remaining at 1) ignore the
receiving data because their MSBs (Bit8 or <RB8>) are set to 0 to disable the
interrupt INTRX0.
The slave controllers (WU = 0) can transmit data to the master controller, and it is
possible to indicate the end of data receiving to the master controller by this
transmission.
Start
Start
Bit0
Bit0
1
1
Select code of slave controller
93CS20-167
2
2
3
3
Data
4
4
5
5
6
6
7
7
Bit8
8
1
0
Stop
Stop
TMP93CS20
2004-02-10