TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 178

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(4) Slave address and address recognition mode specification
(5) Master/slave selection
address, set I2CAR<ALS> to 0 and set the slave address to the I2CAR<SA6:0>.
recognize the slave address, set <ALS> to 1. When the TMP93CS20 used in the free
data format, the slave address and the direction bit are not recognized. They are
handled as data just after generation of start conditions.
cleared to 0 by the hardware after a stop condition on a bus is detected or arbitration is
lost.
b.
To operate the TMP93CS20 in the addressing format which recognizes the slave
To operate the serial bus interface circuit in the free data format which does not
Set SBICR2<MST> to 1 for operating the TMP93CS20 as a master device. <MST> is
Clock synchronization
slow processing device when a transfer is performed between devices which have
different process speed.
line of the bus is low level in the serial bus interface circuit. The serial bus
interface circuit waits counting a clock pulse in high level until the SCL line of the
bus is high level. When the SCL line of the bus is high level, the serial bus
interface circuit starts counting during high level. The clock synchronization
function holds clocks which are output from the serial interface circuit to be high
level.
one bit basis.
speed of the slave device.
SCL pin (Master device)
SCL pin (Slave device)
SCL (Bus)
The I
The clock synchronization functions when the SCL pin is high level and the SCL
The slave device can stop the clock output of the master device on one word or
Additionally, the transfer speed by the master device matches to the process
2
C bus has a clock synchronization function to meet the transfer speed to a
Figure 3.10.8 Clock Synchronization
93CS20-176
Wait
Start counting high-level width
of a clock pulse
TMP93CS20
2004-02-10