TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 162

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(9) Transmission buffer
(10) Parity control circuit
(11) Error flag
written from the CPU from the least significant bit (LSB) in order. When all bits are
shifted out, the transmission buffer becomes empty and generates INTTX0 interrupt.
transmit and receive data with parity. However, parity can be added only in 7-bit
UART or 8-bit UART modes. With SC0CR<EVEN> register, even or odd parity can be
selected.
the transmission buffer SC0BUF. The data is transmitted after the parity bit is stored
in SC0BUF<TB7> when in 7-bit UART mode or in SC0MOD<TB8> when in 8-bit
UART mode. <PE> and <EVEN> must be set before the transmission data is written to
the transmission buffer.
data is transferred to receiving buffer 2 (SC0BUF), and then compared with
SC0BUF<RB7> when in 7-bit UART mode and with SC0MOD<RB8> when in 8-bit
UART mode. If they are not equal, a parity error occurs and SC0CR<PERR> flag is set.
1.
2.
3.
The transmission buffer (SC0BUF) shifts out and sends the transmission data
When the serial channel control register SC0CR<PE> is set to 1, it is possible to
For transmission, parity is automatically generated according to the data written in
For receiving, data are shifted in the receiving buffer 1, the parity is added after the
Three error flags are provided to increase the reliability of receiving data.
Overrun error <OERR>
stored in receiving buffer 2 (SC0BUF), an overrun error will occur.
Parity error <PERR>
compared with the parity bit received from RXD pin. If they are not equal, a parity
error occurs.
Framing error <FERR>
majority is 0, a framing error occurs.
If all bits of the next data are received in receiving buffer 1 while valid data is
The parity generated for the data shifted in receiving buffer 2 (SC0BUF) is
The stop bit of received data is sampled three times around the center. If the
93CS20-160
TMP93CS20
2004-02-10