AMD-762 Advanced Micro Devices, AMD-762 Datasheet - Page 106

• Manufacturer Part Number: AMD-762
• Description: System Controller
• Manufacturer: Advanced Micro Devices

AMD-762™ System Controller Data Sheet
7.1
Table 35.
94
AD[31:30]
AD[29]
AD[28]
AD[27:26]
Signal
Initialization Pinstrapping
Initialization Pinstrapping
Type
I
I
I
I
ClkSpeed
These pinstraps are used to define the clock speed of the AMD Athlon™ processor system
bus and DDR SDRAM interface, and are encoded as follows:
00: 100 MHz
01: 66 MHz (test and debug only)
10: Reserved
11: 133 MHz
The value of this pinstrap can be read in the Configuration Status register (Dev 0:F0:0x88).
PLL Reset
This pin must be driven Low when using the PLL bypass test mode. This pin is also
optionally used in test modes as described in Chapter 3. A pullup resistor is required on
this pinstrap for normal operation.
SysClkThresh
This pin functions as the AMD Athlon processor system bus threshold range select for the
system clock input receiver. When Low, the system clock input senses thresholds between
0.6 V and 1.0 V. When High, the inputs sense thresholds between 1.0 V and 1.4 V.
The value of this pinstrap can be read in the Configuration Status register (Dev 0:F0:0x88).
Length 1
This bit field selects the CPU 1 physical AMD Athlon processor system bus length:
00: Short, non-slot A
01: Single slot A or “close”
10: Far dual slot A
11: Farthest possible slot A
See the AMD Athlon System Bus Design Guide, order# 22666, for details of the bus length
assumptions used in the bus timing calculations. The value of this pinstrap can be read in
the Configuration Status register (Dev 0:F0:0x88).
The AMD-762 system controller requires various pinstrapping
options to define the SIP stream returned to the AMD Athlon
processor aft er reset , as well as to define specific AMD-762
system controller operating parameters. The pinstraps are set
by 10K pullup or pulldown resistors attached externally to PCI
bus pins, and they are sampled during reset. Unless otherwise
defined, strapping options are enabled when pulled High,
disabled when pulled Low. BIOS can read the value latched on
most of these pinstraps in the Configuration Status register
(Dev 0:F0:0x88). See Table 35 for a description of the pinstraps.
Preliminary Information
Signal Descriptions
Description
24416C— December 2001
Chapter 7