AMD-762 Advanced Micro Devices, AMD-762 Datasheet - Page 30

• Manufacturer Part Number: AMD-762
• Description: System Controller
• Manufacturer: Advanced Micro Devices

AMD-762™ System Controller Data Sheet
2.3.3
2.3.4
18
PCI Parity/ ECC Errors
PCI Configuration
Th e AMD-762 syst em con t r olle r uses PCI configu r a t i on
m e ch anism #1 to s e l e c t all of t h e op tions ava i l ab l e for
interaction with the processor, DRAM, and the PCI bus. This
mech a n i sm is define d in t h e PCI Local Bus Specificat ion,
Revision 2.2. All configu ration functions for the AMD-762
syst em cont roller are performed by using two I/O-mapped
configuration registers —IO_CNTRL (I/O address 0CF8h) and
IO_DATA (I/O address 0CFCh).
These two registers are used to access all the other internal
configuration registers of the AMD-762 system controller. The
AMD-762 system controller decodes accesses to these two I/O
addresses and handles them internally. A read to a nonexistent
configuration register returns a value of FFh. Accesses to all
other I/O addresses are forwarded to the PCI bus as regular I/O
cycles. Read and write cycles involving the AMD-762 system
controller configuration registers are only distinguished by the
address and command that is sent.
The AMD-762 system con t roller implements the following
configuration spaces:
n Device 0:Function 0 (host bridge configuration registers)
n Device 0:Function 1 (DDR I/O and PDL configuration)
n Device 1:Function 0 (PCI-PCI bridge, AGP configuration)
The Device 0:Function 1 space is disabled by default, and must
be enabled by wr iting to a specific bit in the PCI Control
register (Dev 0:F0:0x4C). The normal reserved PCI header
space (0x00-0x3F) in this function returns all 1s.
The AMD-762 system controller indicates t hat an ECC error
occurred on the memory bus by se t t ing a bit in the status
register and optionally asserting the PCI SERR# signal. This
action results in the error being reported by the Southbridge.
The AMD-762 system controller does not check parity on the
PCI bus. The status bit (Dev 0:04h, bit 31) is always 0.
Preliminary Information
Functional Operation
24416C—December 2001
Chapter 2