AMD-762 Advanced Micro Devices, AMD-762 Datasheet - Page 110

• Manufacturer Part Number: AMD-762
• Description: System Controller
• Manufacturer: Advanced Micro Devices

AMD-762™ System Controller Data Sheet
Table 36.
7.3
98
GNT[6]# /AGPCLKOUT
GNT[5]# /SYSCLKOUT
GNT[3]# /DDR_NAND
GNT[2]# /PCI_NAND
GNT[1]# /AGP_NAND
GNT[0]# /CPU_NAND
IRDY# /TEST_RST#
TRDY# /SCAN_EN#
PAR/PLL_TEST#
Primary/Secondary
Pin Name
Pin Multiplexing Options
Pin States at Reset
PCI bus grant #6
PCI bus grant #5
PCI bus grant #3
PCI bus grant #2
PCI bus grant #1
PCI bus grant #0
PCI bus IRDY# pin
PCI bus TRDY# pin
PCI bus PAR (parity) pin
n IRDY# pin for the TEST_RESET# function
n PAR pin for PLL output test mode.
These functions are described in detail in Chapter 3.
The AMD-762 system controller default pin states are defined in
Tab l e 37 on page 99. Th e s e a re liste d for all o u t p u t a n d
bidirectional pins in the power-on reset state (reset) as well as
the ACPI S1 and S3 power management states. Refer to “Power
Management” on page 25 for details of the S1 and S3 modes.
No t e t h a t m o s t AMD-762 s y s t e m c on t r ol l e r i n t e r n a l
configuration registers are initialized to a known value when
RESET# is asserted. To accommodate the ACPI S3 (suspend to
RAM) powe r manage m e n t st a t e , t h e memor y c o n t rolle r
r e g i s t e r s a re n o t i n i t i a l i ze d a t p owe r -u p a n d m u s t b e
programmed by BIOS following the first power-up. For further
details, refer to Chapter 2, “Functional Operation” and the
AMD-762™ System Controller Software/BIOS Design Guide,
order# 24462.
Primary Function
Preliminary Information
Signal Descriptions
APLL clock output for PLL test. Refer to Chapter 3
for details of this function.
SPLL clock output for PLL test. Refer to Chapter 3
for details of this function.
Output of the DDR DRAM interface NAND tree.
Output of the PCI bus interface NAND tree.
Output of the AGP interface NAND tree.
Output of the AMD Athlon™ processor system
bus interface NAND tree.
Reset pin dedicated to PLL clock dividers. Refer to
Chapter 3 for details of this function. Used only
for PLL testing.
Enables scan testing when TEST# is asserted. Not
used in normal operation.
Enables clock testing when TEST# is asserted. The
values on pinstraps AGPClock_Mux[2:0] and
SysClock_Mux[2:0] strapping pins select the clock mux
inputs. Refer to Chapter 3 for details of PLL test mode.
Secondary Function
24416C— December 2001
Chapter 7