AMD-762 Advanced Micro Devices, AMD-762 Datasheet - Page 22

• Manufacturer Part Number: AMD-762
• Description: System Controller
• Manufacturer: Advanced Micro Devices

AMD-762™ System Controller Data Sheet
2.2
10
Memory Interface
The AMD-762 memory controller ar bit rates and optimizes
i n comin g memory re q u ests, h a n d les ECC a n d Gra p h i cs
Address Remapping Table (GART), and controls up to four
double-data-rate (DDR) SDRAM DIMMs.
The AMD-762 system controller memory interface is designed
to support regist e red DDR DIMMs. Up to fou r regis t e re d
DIMMs can be supported by the AMD-762 system controller.
The AMD-762 system controller supports 64-Mbit, 128-Mbit,
256-Mbit, and 512-Mbit DDR devices. Device widths of x4, x8,
and x16 are supported. Mixed banks are supported, meaning
that a x8 DIMM can coexist with x4 and x16, etc.
Refer to Table 1 on page 11 for the total memory sizes for
various registered DIMM configurations. A total of 4 Gbytes is
supported.
DDR timing parameters are programmable via the AMD-762
system controller’s memory controller configuration registers,
a l l owing su p p o r t of diffe rent DIMM configura t i o n s a n d
loading. Refresh is also programmable, with support of various
r e f re s h ra tes as we ll a s t h e a b ility t o q u e u e u p t o fou r
outstanding re freshes. Clock pairs can also be selectively
disabled to unpopulated DIMM slots via configuration register
bits in the memory controller.
The memory controller supports up to four open pages in the
active chip select. All pages in a chip select are closed when an
acce ss to anot h e r ch ip sel e c t i s d e t e c t e d . Memor y p a ge
o p e ration can be fur t h e r opti mize d by p r ogr a mming t h e
n u m b e r o f i d l e cy c l e s t o a b a n k b e f o r e t h e b a n k i s
automatically precharged.
Preliminary Information
Functional Operation
24416C—December 2001
Chapter 2