AMD-762 Advanced Micro Devices, AMD-762 Datasheet - Page 57

• Manufacturer Part Number: AMD-762
• Description: System Controller
• Manufacturer: Advanced Micro Devices

24416C—December 2001
3.4
Chapter 3
Clock Output Test Mode
option s for PLL bypass mode as listed in Ta ble 6 below.
Because the AMD-762 system controller internal logic normally
uses clocks t h a t a re 2x the SYSCLK i n p u t an d 2x/4x t h e
AGPCLK input, the PLL bypass mode requires that either 2x or
4x clocks be driven in this mode, but they can be driven at a
mu ch lowe r fre q u e n cy for t e s t p u rposes. Note that wh e n
operating in this mode, the minimum clock frequency most
likely will be dictated by the surrounding logic, such as the
DDR interface.
Table 6.
The PLL reset function can be invoked by asserting a Low on
the PCI IRDY# pin This procedure provides a synchronous
reset for the clocking, but probably is not required when using
this test mode for motherboard debug.
Note: AD[29] must be pulled Low when entering PLL bypass test
The clock output test mode provides external visibility of the
two PLLs used to generate the clocks for the processor/memory
and AGP clock d omains. In this test mode, the PLLs a re
running, and the output clocks are driven to GNT[6:5]# pins.
System designers that intend to make use of this test feature
should provide 0-ohm resistors on these pins to isolate the PCI
peripherals when observing the clocks.
This test mode is entered by the Low assertion of the TEST#
p i n while p u l ling the PCI bu s PAR pin Low. Add it i onal
pinstraps are then used to select the various clock outputs as
illustrated in Table 7 on page 46.
AGP-4x Testing
Normal
Mode
mode to enable the PLL reset function capability.
Preliminary Information
Clocking Options in PLL Bypass Test Mode
C/ BE[1]#
0
1
Test
SYSCLK
2x
2x
AGPCLK
AMD-762™ System Controller Data Sheet
2x
4x
PLLs bypassed, drives a 2x clock
to internal divider, and resulting
1x clock to internal logic.
Same as above, except allows 4x
clock to accommodate 4x AGP
testing.
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