RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 117

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
DPLL_ERR_EN
FAST_ACQ
PHD_MODE
RCLK_INV
N8953BDSB
0xF4—Command Register 7 (CMD_7)
PRA_EN
7
FEBE_POLARITY
DPLL Error Interrupt Enable—Enables DPLL errors to request RX_ERR interrupt when an
overflow or underflow condition occurs at the phase detector output. DPLL errors are latched
and reported in ERR_STATUS [addr 0x3C] regardless of DPLL_ERR_EN.
Fast Acquisition—Enables DPLL fast frequency acquisition by instructing the NCO to reuse
the residual phase calculated prior to a DPLL error condition. The phase detector initializes
according to PHD_MODE (see below) while the NCO continues tracking the last known
phase, thus widening the DPLL bandwidth. FAST_ACQ is preferable while the master framer
remains IN_SYNC. To avoid RCLK frequency violations, FAST_ACQ may be disabled when
the master framer is OUT_OF_SYNC.
NOTE:
Phase Detector Init Mode—Selects a method to initialize the phase detector window when a
DPLL error occurs. The phase detector can either initialize to the center of the phase window
or opposing edge, not initialize at all, or use the programmed DPLL_PINI [addr 0xDB] value.
NOTE:
Receive Output Clock Inverted—Enables binary inversion of the clock selected by
RCLK_SEL [CMD_2; addr 0xE6].
6
If the system determines that the DPLL is not locked, then the MPU must assert
DPLL _RST [addr 0xF6] to force the DPLL to reload DPLL_RSID [addr 0xD5]. The
system may monitor DPLL tracking by reading RESID_OUT [addr 0x28] or by
checking DPLL_ERR [ERR_STATUS; addr 0x3C].
Disabling the phase detector is not recommended as the error output can remain
saturated without reporting the DPLL error status or generating DPLL interrupts.
NCO_SCALE
5
0 = DPLL errors do not generate a RX_ERR interrupt
1 = DPLL errors generate a RX_ERR interrupt
0 = Disable fast acquisition
1 = Enable fast acquisition
PHD_MODE
RCLK_INV
00
01
10
11
0
1
4
Conexant
DPLL_PINI value
Opposing edge of phase window
Disabled (infinite phase window)
Center of phase window
RCLK = Clock selected by RCLK_SEL
RCLK = Inverted clock selected by RCLK_SEL
3
PHD_MODE
Phase Detector Initialization
2
FAST_ACQ
4.11 Common Command
1
4.0 Registers
DPLL_ERR_EN
0
4-49