RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 36
RS8953
Manufacturer Part Number
RS8953
Description
High-bit-rate Digital Subscriber Line (hdsl) Channel unit
Manufacturer
Conexant Systems, Inc.
Datasheet
1.RS8953.pdf
(173 pages)
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3.0 Circuit Descriptions
3.2 PCM Channel
Figure 3-3. PCM Channel Block Diagram
3-4
RMSYNC
TMSYNC
INSDAT
INSERT
MSYNC
EXCLK
DROP
RSER
TSER
RCLK
TCLK
3.2 PCM Channel
The Pulse Code Multiplexed (PCM) channel displayed in
independent transmit and receive formatter circuits to control the flow of serial
data between PCM and HDSL channels, to establish alignment between PCM and
HDSL frames, and maintain synchronization between PCM and HDSL clocks.
Framed serial data consists of a variable number of multiplexed 8-bit timeslots,
plus an optional framing bit (F-bit), a variable number of PCM frames repeated to
form a PCM multiframe, and a variable number of multiframes concatenated to
form a PCM 6 ms frame. T1, E1, or custom Nx64 frame formats are selected by
programming the PCM Formatter Registers (see
of bits per frame [FRAME_LEN; addr 0xC8], frames per multiframe [MF_LEN;
addr 0xC6], and multiframes per 6 ms frame [MF_CNT; addr 0xC7]. Unframed
serial data is selected in the same manner; however, the number of bits per frame
act as a single channel rather than individual timeslots and can support PCM
frame lengths that are not integer multiples of 8-bits.
period based on the Transmit Clock (TCLK) and Receive Clock (RCLK). PCM
timebases are programmed to equal approximately the HDSL 6 ms frame period
defined by the HDSL Frame Length [HFRAME_LEN; addr 0xCA] in relation to
the master HDSL channel’s Bit Clock (BCLKn). The resultant PCM and HDSL
6 ms frame intervals are used to establish alignment between PCM and HDSL
frames, to maintain synchronization between transmit clocks by performing bit
stuffing, and to recover PCM receive clock by comparing phase offset between
frames.
In framed or unframed applications, PCM timebases create a 6 ms frame
Recovered
Clock
Transmit Formatter
Receive Formatter
DPLL
(Data and Sync)
Conexant
Loopback
Master
Sync
CH1 Transmit (Data and Sync)
CH2 Transmit
CH3 Transmit
PCM 6 ms Sync
CH1 Receive (Data and Sync)
CH2 Receive
CH3 Receive
Table
4-4) to define the number
Figure 3-3
RS8953B/8953SPB
HDSL Channel Unit
N8953BDSB
consists of
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