RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 49

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
Figure 3-15. PCM and HDSL Loopbacks
N8953BDSB
TSER
RSER
PP_LOOP
PCM Channel
3.4 Loopbacks
The RS8953B provides multiple PCM and HDSL loopbacks, as shown in
Figure
Loopback activation in the test direction does not disrupt the through data path in
the non-test direction. Data path options (refer to
replace data in the non-test direction with fixed or PRBS test patterns.
shows the loopback controls which are designated by initials corresponding to
test direction and the channel from which data is looped.
multiframe sync signals to the test direction. In these loopback modes, the PCM
transmit and receive clocks are not automatically switched to the test direction.
The PCM transmit and receive clocks must be properly configured for these
loopback modes to operate.
mapped require that PH_LOOP mode be enabled to complete PCM channel
loopback on the HDSL side. Also, the same tap must be used for the RS8953B
scrambler and descrambler, or both the RS8953B scrambler and descrambler
must be disabled.
transceivers must be enabled. Different tap must be used in each direction. This is
required to prevent the exact same data to be sent in both directions. If the exact
same data is sent in both directions, the echo canceler in the HDSL transceivers
will consider the data an echo and cancel the data. Also, the same tap must be
used for the RS8953B scrambler and descrambler, or both the RS8953B
scrambler and descrambler must be disabled.
PP_LOOP and HP_LOOP automatically switch both PCM data and PCM
When performing PH_LOOP, all HDSL channels that have payload data
When performing HH_LOOP, the scrambler and descrambler in the HDSL
HP_LOOP
3-15. The output towards which data is looped is called the test direction.
Conexant
PH_LOOP
PH_LOOP
PH_LOOP
HDSL Channel 1
HDSL Channel 2
HDSL Channel 3
Table
HH_LOOP
HH_LOOP
HH_LOOP
4-7) are provided to
3.0 Circuit Descriptions
3.4 Loopbacks
Table 3-1
TDAT1
RDAT1
TDAT2
RDAT2
TDAT3
RDAT3
3-17