RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 37

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
3.2.1 PCM Transmit
Figure 3-4. PCM Transmit Block Diagram
N8953BDSB
TMSYNC
PCM_FLOAT
RMSYNC
INSDAT
INSERT
MSYNC
RSER
TSER
RCLK
TCLK
TCLK_SEL
The PCM transmit formatter shown in
serial data on the TSER and INSDAT inputs. Both inputs are sampled on the
clock edge selected by TCLK_SEL [CMD_2; addr 0xE6] according to the format
of the PCM Multiframe Sync (MSYNC) output. The PCM transmit timebase
outputs MSYNC to mark two clock cycles before the PCM input sample point of
bit 0, frame 0. The timebase either references the system’s Transmit Multiframe
Sync (TMSYNC) input or supplies MSYNC without regard to TMSYNC, as
controlled by the PCM_FLOAT setting [CMD_2; addr 0xE6].
two TCLK bit positions.
outputs MSYNC according to the PCM formatter register values: FRAME_LEN,
MF_LEN, and MF_CNT. In this case, MSYNC acts as PCM bus master and
supplies a multiframe sync reference to the system as illustrated in
without a specific TMSYNC relationship.
Figures 3-5
with respect to TMSYNC by programming the number of bit delays
[TFRAME_LOC; addr 0xC0] from TMSYNC’s rising edge to bit 0 of the PCM
frame. In addition, it locates the frame 0 input sample point by programming the
additional number of frame delays [TMF_LOC; addr 0xC2] needed to mark the
first frame of a PCM multiframe.
HP_LOOP
The MSYNC leads the sampling of bit 0, frame 0, on TSER and INSDAT by
If PCM_FLOAT is active, the transmit timebase ignores TMSYNC and
If PCM_FLOAT is inactive, MSYNC is aligned to TMSYNC (as shown in
Delay
Bit
and 3-6). The system locates the sampling point of bit 0, frame 0,
PCM Transmit Timebase
Length
Frame
Conexant
Previous
PRBS
Routing Table
Length
MF
Figure 3-4
Frame
Delay
TFIFO 1
TFIFO 2
TFIFO 3
accepts framed or unframed
TFIFO_WL 1
TFIFO_WL 2
TFIFO_WL 3
Count
MF
3.0 Circuit Descriptions
= Command Register Bit
TFIFO_RST
Figure
3.2 PCM Channel
CH1 DATA
CH2 DATA
CH3 DATA
CH1 TSYNC
CH2 TSYNC
CH3 TSYNC
PCM
PCM TCLK
6 MS
3-5, but
3-5