RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 63

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
Figure 3-24. Threshold Correlation Effect on Expected Sync Locations
N8953BDSB
3.5.2.3 Descrambler
SYNC Pattern
SYNC Pattern < THRESH_CORR
0
0
SYNC_ERRORED
SYNC_ERRORED
1
1
THRESH_CORR
–2q
–1q
words are detected, or regresses to the Sync Errored state if sync pattern errors are
found. During Sync Errored states, the number of matching bits from each
comparison of received sync word and programmed sync word patterns must
meet or exceed the programmed pattern match tolerance specified by
THRESH_CORR [RCMD_2; addr 0x61]. If the number of matching bits falls
below tolerance, the framer expands the locations searched to quats on either side
of the expected location, as shown in
error and changing to the Sync Errored state, the framer passes through a
programmable number of intermediate Sync Errored states, before entering the
Out Of Sync state. STATE_CNT increments for each frame in which sync is not
detected until the count reaches the LOSS_SYNC criteria [RCMD_1; addr 0x60]
and the framer enters the Out Of Sync state. If at any time during the Sync
Errored state the framer detects a completely correct sync word pattern at one of
the valid frame locations, then the framer returns to the In Sync state. The ETSI
standard recommends the REACH_SYNC = 2 and LOSS_SYNC = 6 framing
criteria.
The descrambler operates at the BCLKn bit rate on all HDSL receive data, except
for the 14-bit SYNC words and 4 STUFF bits. The MPU enables the descrambler
by setting the DSCR_EN bit and selects the descrambler algorithm via
DSCR_TAP [RCMD_2; addr 0x61]. Two descrambling algorithms are
implemented as follows:
6 ms
6 ms
After entering In Sync, the framer either remains In Sync as successive sync
• In the HTU-R to HTU-C direction, the polynomial shall be
• In the HTU-C to HTU-R direction, the polynomial shall be
+1q
+2q
SYNC_ERRORED
SYNC_ERRORED
X
X
–23
–23
2
2
X
X
–18
–5
–3q
1, where
Conexant
1, where
–1q
–1q
12 ms
12 ms
+1q
+1q
SYNC_ERRORED
SYNC_ERRORED
+3q
is equal to modulo 2 summation.
is equal to modulo 2 summation.
3
3
Figure
–4q
–2q
–1q
18 ms
18 ms
3-24. After detecting a sync pattern
+1q
+2q
+4q
q = 2 Bits = 1 Quat
= Search Location
3.0 Circuit Descriptions
3.5 HDSL Channel
T
T
3-31