RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 47

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
Figure 3-14. DPLL Block Diagram
N8953BDSB
MCLK
Phase Detector
CH2 RSYNC
PLL
CH1 RSYNC
CH3 RSYNC
x PLL_MUL
MASTER_SEL
PLL_DIS
3.3 Clock Recovery DPLL
The Digital Phase Locked Loop (DPLL) shown in
PCM Receive Clock (RCLK) from a 60–80 MHz High Frequency Clock
(HFCLK). HFCLK is developed by analog PLL multiplication of the MCLK
input frequency, or HFCLK is applied directly to the MCLK input (see
PLL_MUL and PLL_DIS in CMD_1; addr 0xE5). The analog PLL requires
external loop filter components and connections as shown in Figure 6-1. HFCLK
must be in the range of 60–80 MHz, but requires no specific frequency or phase
relationship to PCM or HDSL clocks. Open or closed loop operation is selected
by DPLL_NCO [CMD_5; addr E9].
HDSL 6ms
PCM 6ms
÷
PLL_DIV
DPLL_RST
÷ 4
Start
Stop
DPLL_NCO
CNT
RST
HFCLK
÷
GCLK
Conexant
MF_CNT
~ 15-20 MHz
~ 60-80 MHz
~ 12 MHz
DPLL Filter
DPLL_GAIN
÷
INIT
MF_LEN
Z -1
NCO
÷
FRAME_LEN
÷ N-1
÷ N
÷ N
÷ N+1
÷ N+1
÷ N+2
Figure 3-14
SUM
Z -1
DPLL_FACTOR
OVF
DPLL_RESID
3.0 Circuit Descriptions
3.3 Clock Recovery DPLL
synthesizes the
÷ 2
RCLK
SCLK
3-15