RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 130

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

4.0 Registers
4.14 Common Status
RX1-RX3
TX_ERR
RX_ERR
RESID_OUT[15:0]
This register contains data written to IMR [addr 0xEB] and is provided as an MPU read back register. The MPU
interrupt service routine can use the IMR read value to mask read data from the IRR and to avoid processing of
masked interrupts.
4-62
0x28—DPLL Residual Output (RESID_OUT_LO)
0x20—DPLL Residual Output (RESID_OUT_HI)
0x30—Interrupt Mask Register (IMR)
7
7
Receive HDSL 6 ms Frame Interrupt—Reported coincident with the start of the receive 6 ms
frame for the respective HDSL channel. This allows the MPU to synchronize read access of
the real time receive status (see
channel (see
Transmit Error Interrupt—The transmit stuffing and TFIFO errors from all enabled error
sources are logically ORed to form TX_ERR. When active, the MPU reads the Error Status
Register [ERR_STATUS; addr 0x3C] to determine which source caused the interrupt.
Receive Error Interrupt—Framer state transitions, RFIFO errors, CRC and FEBE counter
overflows, and DPLL errors from all enabled error sources are logically ORed to form
RX_ERR. When active, the MPU reads the Error Status Register [ERR_STATUS; addr 0x3C]
to determine which source caused the interrupt.
DPLL Residual Output—The NCO’s residual phase output equals the synthesized phase
needed to construct half-cycle of the recovered clock, given as a fractional result, in units of
HFCLK. During DPLL closed loop operation, the RESID_OUT value should converge to
approximately equal the programmed DPLL_RESID [addr 0xD6] value. The MPU can
calculate the recovered clock frequency by substituting the measured value of RESID_OUT in
the synthesis equation, and solving for RCLK. RESID_OUT is updated coincident with the
RXn interrupt (where n = master HDSL channel number) and is provided for diagnostics only.
6
6
Table
5
5
4-11).
0 = No interrupt
1 = Receive frame interrupt
0 = No interrupt
1 = Transmit error interrupt
0 = No interrupt
1 = Receive error interrupt
4
4
RESID_OUT[15:8]
Table
RESID_OUT[7:0]
Conexant
4-10) and the DPLL status of the master HDSL receive
3
3
2
2
RS8953B/8953SPB
1
1
HDSL Channel Unit
N8953BDSB
0
0