RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 139

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RS8953

Manufacturer Part Number
RS8953
Description
High-bit-rate Digital Subscriber Line (hdsl) Channel unit
Manufacturer
Conexant Systems, Inc.
Datasheet

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RS8953B/8953SPB
HDSL Channel Unit
AIS
RST_E_CNT
The value of this register is only relevant if the corresponding MODE bit of TX_PRA_CTRL0 is set. A new
written value takes effect starting with the next PCM multiframe, following the register write access cycle
completion.
8 consecutive multiframes.
Sa
Sa
Sa
A_MASK
SA5_MASK
SA6_MASK
The value of this register is used to enable the accommodation of the RS8953B to any TMSYNC signal shape.
When programmed to 0x00, the PRA circuitry assumes that the positive edge of the TMSYNC input signal
coincides with the first bit of an PCM framer.
N8953BDSB
0x72—PRA Transmit Bits Buffer 1 (TX_BITS_BUFF1)
0x73—PRA Transmit TMSYNC offset Register (TX_PRA_TMSYNC_OFFSET)
4
7
8
An in-band code is reported as detected when the pattern in the Sa6, Sa5, AND A fields remain constant for
7
7
SA6_MASK
Enables to override all 32 slots of an PCM frame except slot 0 transmitted towards the HDSL
link, with a constant pattern:
NOTE:
Clears the TX_E counter
NOTE:
The new value to be inserted into the Sa
direction.
The new value to be inserted into the Sa
direction.
The new value to be inserted into the Sa
direction.
Determines whether the pattern in the A-bit field must remain constant for 8 consecutive
multiframes for an in-band code to be reported as detected.
Determines whether the pattern in the SA5 field must remain constant for 8 consecutive
multiframes for an in-band code to be reported as detected.
Determines whether the pattern in the SA6 field must remain constant for 8 consecutive
multiframes for an in-band code to be reported as detected.
6
6
AIS enables to achieve framed AIS. To achieve unframed arbitrary AUX pattern
generation, use the existing feature of the channel unit.
The value of this register takes effect starting with the next PCM multiframe
following the write access cycle completion.
SA5_MASK
5
5
0 = Disable (Normal)
1 = 0xFF
0 = Counter enabled
1 = Clear the E transmit counter
TX_PRA_TMSYNC_OFFSET[7:0]
A_MASK
4
4
Conexant
4
7
8
location of the data stream, in the PCM to HDSL
location of the data stream, in the PCM to HDSL
location of the data stream, in the PCM to HDSL
3
3
Sa
2
2
8
Sa
4.16 PRA Transmit Write
1
1
7
4.0 Registers
Sa
0
0
4
4-71

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